Yier Jin

According to our database1, Yier Jin authored at least 110 papers between 2006 and 2019.

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Bibliography

2019
On the Approximation Resiliency of Logic Locking and IC Camouflaging Schemes.
IEEE Trans. Information Forensics and Security, 2019

SoC interconnection protection through formal verification.
Integration, 2019

RTL-PSC: Automated Power Side-Channel Leakage Assessment at Register-Transfer Level.
Proceedings of the 37th IEEE VLSI Test Symposium, 2019

On the Impossibility of Approximation-Resilient Circuit Locking.
Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2019

QIF-Verilog: Quantitative Information-Flow based Hardware Description Languages for Pre-Silicon Security Assessment.
Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2019

KC2: Key-Condition Crunching for Fast Sequential Circuit Deobfuscation.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

When Capacitors Attack: Formal Method Driven Design and Detection of Charge-Domain Trojans.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

NETA: when IP fails, secrets leak.
Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019

Resilient Distributed Filter for State Estimation of Cyber-Physical Systems Under Attack.
Proceedings of the 2019 American Control Conference, 2019

2018
Enabling Security-Enhanced Attestation With Intel SGX for Remote Terminal and IoT.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2018

The Old Frontier of Reverse Engineering: Netlist Partitioning.
J. Hardware and Systems Security, 2018

Internet-of-Things Security and Vulnerabilities: Taxonomy, Challenges, and Practice.
J. Hardware and Systems Security, 2018

Development and Evaluation of Hardware Obfuscation Benchmarks.
J. Hardware and Systems Security, 2018

Microarchitectural Minefields: 4K-Aliasing Covert Channel and Multi-Tenant Detection in Iaas Clouds.
Proceedings of the 25th Annual Network and Distributed System Security Symposium, 2018

Hardware Trojan Detection and Functionality Determination for Soft IPs.
Proceedings of the 3rd IEEE International Verification and Security Workshop, 2018

TimingSAT: Decamouflaging Timing-based Logic Obfuscation.
Proceedings of the IEEE International Test Conference, 2018

Security for safety: a path toward building trusted autonomous vehicles.
Proceedings of the International Conference on Computer-Aided Design, 2018

SIN2: Stealth infection on neural network - A low-cost agile neural Trojan attack methodology.
Proceedings of the 2018 IEEE International Symposium on Hardware Oriented Security and Trust, 2018

R2D2: Runtime reassurance and detection of A2 Trojan.
Proceedings of the 2018 IEEE International Symposium on Hardware Oriented Security and Trust, 2018

Cross-Lock: Dense Layout-Level Interconnect Locking using Cross-bar Architectures.
Proceedings of the 2018 on Great Lakes Symposium on VLSI, 2018

Device attestation: Past, present, and future.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

Power-based side-channel instruction-level disassembler.
Proceedings of the 55th Annual Design Automation Conference, 2018

Security analysis and enhancement of model compressed deep learning systems under adversarial attacks.
Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018

PT-spike: A precise-time-dependent single spike neuromorphic architecture with efficient supervised learning.
Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018

Hardware control flow integrity.
Proceedings of the Continuing Arms Race: Code-Reuse Attacks and Defenses, 2018

2017
Silicon Demonstration of Hardware Trojan Design and Detection in Wireless Cryptographic ICs.
IEEE Trans. VLSI Syst., 2017

Hardware Trojan Detection Through Chip-Free Electromagnetic Side-Channel Statistical Analysis.
IEEE Trans. VLSI Syst., 2017

Automatic Code Converter Enhanced PCH Framework for SoC Trust Verification.
IEEE Trans. VLSI Syst., 2017

Introduction to Cyber-Physical System Security: A Cross-Layer Perspective.
IEEE Trans. Multi-Scale Computing Systems, 2017

Data Secrecy Protection Through Information Flow Tracking in Proof-Carrying Hardware IP - Part I: Framework Fundamentals.
IEEE Trans. Information Forensics and Security, 2017

Eliminating the Hardware-Software Boundary: A Proof-Carrying Approach for Trust Evaluation on Computer Systems.
IEEE Trans. Information Forensics and Security, 2017

Data Secrecy Protection Through Information Flow Tracking in Proof-Carrying Hardware IP - Part II: Framework Automation.
IEEE Trans. Information Forensics and Security, 2017

Tunnel FET Current Mode Logic for DPA-Resilient Circuit Designs.
IEEE Trans. Emerging Topics Comput., 2017

Guest Editorial: Security Challenges in the IoT Regime.
J. Hardware and Systems Security, 2017

IP protection through gate-level netlist security enhancement.
Integration, 2017

LAZARUS: Practical Side-Channel Resilient Kernel-Space Randomization.
Proceedings of the Research in Attacks, Intrusions, and Defenses, 2017

Hardware-Assisted Cybersecurity for IoT Devices.
Proceedings of the 18th International Workshop on Microprocessor and SOC Test and Verification, 2017

Revisit sequential logic obfuscation: Attacks and defenses.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

HA2lloc: Hardware-Assisted Secure Allocator.
Proceedings of the Hardware and Architectural Support for Security and Privacy, 2017

Exploitations of wireless interfaces via network scanning.
Proceedings of the 2017 International Conference on Computing, 2017

ATRIUM: Runtime attestation resilient under memory attacks.
Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017

MT-spike: A multilayer time-based spiking neuromorphic architecture with temporal error backpropagation.
Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017

AppSAT: Approximately deobfuscating integrated circuits.
Proceedings of the 2017 IEEE International Symposium on Hardware Oriented Security and Trust, 2017

Circuit Obfuscation and Oracle-guided Attacks: Who can Prevail?
Proceedings of the on Great Lakes Symposium on VLSI 2017, 2017

Cyclic Obfuscation for Creating SAT-Unresolvable Circuits.
Proceedings of the on Great Lakes Symposium on VLSI 2017, 2017

An End-to-End View of IoT Security and Privacy.
Proceedings of the 2017 IEEE Global Communications Conference, 2017

Approximate Power Grid Protection Against False Data Injection Attacks.
Proceedings of the 15th IEEE Intl Conf on Dependable, 2017

Estimation of Safe Sensor Measurements of Autonomous System Under Attack.
Proceedings of the 54th Annual Design Automation Conference, 2017

A statistical STT-RAM retention model for fast memory subsystem designs.
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

PCH framework for IP runtime security verification.
Proceedings of the 2017 Asian Hardware Oriented Security and Trust Symposium, 2017

2016
Hardware Trojans: Lessons Learned after One Decade of Research.
ACM Trans. Design Autom. Electr. Syst., 2016

Guest Editorial: Hardware/Software Cross-Layer Technologies for Trustworthy and Secure Computing.
IEEE Trans. Multi-Scale Computing Systems, 2016

Emerging Technology-Based Design of Primitives for Hardware Security.
JETC, 2016

The Changing Computing Paradigm With Internet of Things: A Tutorial Introduction.
IEEE Design & Test, 2016

Security of emerging non-volatile memories: Attacks and defenses.
Proceedings of the 34th IEEE VLSI Test Symposium, 2016

Security validation in IoT space.
Proceedings of the 34th IEEE VLSI Test Symposium, 2016

Quantifying trust in autonomous system under uncertainties.
Proceedings of the 29th IEEE International System-on-Chip Conference, 2016

Panel Security and Privacy in the Age of Internet of Things: Opportunities and Challenges.
Proceedings of the 21st ACM on Symposium on Access Control Models and Technologies, 2016

Automatic RTL-to-Formal Code Converter for IP Security Formal Verification.
Proceedings of the 17th International Workshop on Microprocessor and SOC Test and Verification, 2016

Hardware Security Challenges Beyond CMOS: Attacks and Remedies.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016

Security Challenges in CPS and IoT: From End-Node to the System.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016

Gate-level netlist reverse engineering for hardware security: Control logic register identification.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Emerging challenges in cyber-physical systems: A balance of performance, correctness, and security.
Proceedings of the IEEE Conference on Computer Communications Workshops, 2016

Voting system design pitfalls: Vulnerability analysis and exploitation of a model platform.
Proceedings of the 34th IEEE International Conference on Computer Design, 2016

Provably secure camouflaging strategy for IC protection.
Proceedings of the 35th International Conference on Computer-Aided Design, 2016

Scalable SoC trust verification using integrated theorem proving and model checking.
Proceedings of the 2016 IEEE International Symposium on Hardware Oriented Security and Trust, 2016

How secure is split manufacturing in preventing hardware trojan?
Proceedings of the 2016 IEEE Asian Hardware-Oriented Security and Trust, 2016

Enhancing Hardware Security with Emerging Transistor Technologies.
Proceedings of the 26th edition on Great Lakes Symposium on VLSI, 2016

Using emerging technologies for hardware security beyond PUFs.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

Leverage Emerging Technologies For DPA-Resilient Block Cipher Design.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

Strategy without tactics: policy-agnostic hardware-enhanced control-flow integrity.
Proceedings of the 53rd Annual Design Automation Conference, 2016

AVFSM: a framework for identifying and mitigating vulnerabilities in FSMs.
Proceedings of the 53rd Annual Design Automation Conference, 2016

Invited - Can IoT be secured: emerging challenges in connecting the unconnected.
Proceedings of the 53rd Annual Design Automation Conference, 2016

Security analysis on consumer and industrial IoT devices.
Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016

Netlist reverse engineering for high-level functionality reconstruction.
Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016

2015
Privacy and Security in Internet of Things and Wearable Devices.
IEEE Trans. Multi-Scale Computing Systems, 2015

Hierarchy-Preserving Formal Verification Methods for Pre-silicon Security Assurance.
Proceedings of the 16th International Workshop on Microprocessor and SOC Test and Verification, 2015

Reliable and high performance STT-MRAM architectures based on controllable-polarity devices.
Proceedings of the 33rd IEEE International Conference on Computer Design, 2015

Security Policy Enforcement in Modern SoC Designs.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2015

Cyber-physical systems: A security perspective.
Proceedings of the 20th IEEE European Test Symposium, 2015

Impact assessment of net metering on smart home cyberattack detection.
Proceedings of the 52nd Annual Design Automation Conference, 2015

Pre-silicon security verification and validation: a formal perspective.
Proceedings of the 52nd Annual Design Automation Conference, 2015

HAFIX: hardware-assisted flow integrity extension.
Proceedings of the 52nd Annual Design Automation Conference, 2015

Hardware Design and Verification Techniques for Supply Chain Risk Mitigation.
Proceedings of the 14th International Conference on Computer-Aided Design and Computer Graphics, 2015

2014
Design-for-Security vs. Design-for-Testability: A Case Study on DFT Chain in Cryptographic Circuits.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2014

Real-time trust evaluation in integrated circuits.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

EDA tools trust evaluation through security property proofs.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

FIGHT-Metric: Functional Identification of Gate-Level Hardware Trustworthiness.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014

Embedded System Security in Smart Consumer Electronics.
Proceedings of the 4th International Workshop on Trustworthy Embedded Devices, 2014

Leveraging Emerging Technology for Hardware Security - Case Study on Silicon Nanowire FETs and Graphene SymFETs.
Proceedings of the 23rd IEEE Asian Test Symposium, 2014

2013
A post-deployment IC trust evaluation architecture.
Proceedings of the 2013 IEEE 19th International On-Line Testing Symposium (IOLTS), 2013

Hardware Trojans in wireless cryptographic ICs: silicon demonstration & detection method evaluation.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013

A proof-carrying based framework for trusted microprocessor IP.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013

Cycle-accurate information assurance by proof-carrying based signal sensitivity tracing.
Proceedings of the 2013 IEEE International Symposium on Hardware-Oriented Security and Trust, 2013

Reconciling the IC test and security dichotomy.
Proceedings of the 18th IEEE European Test Symposium, 2013

2012
Proof-Carrying Hardware Intellectual Property: A Pathway to Trusted Module Acquisition.
IEEE Trans. Information Forensics and Security, 2012

Proof carrying-based information flow tracking for data secrecy protection and hardware trust.
Proceedings of the 30th IEEE VLSI Test Symposium, 2012

Exposing vulnerabilities of untrusted computing platforms.
Proceedings of the 30th International IEEE Conference on Computer Design, 2012

Post-deployment trust evaluation in wireless cryptographic ICs.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

2011
PSCML: Pseudo-Static Current Mode Logic.
Proceedings of the 18th IEEE International Conference on Electronics, Circuits and Systems, 2011

Is single-scheme Trojan prevention sufficient?
Proceedings of the IEEE 29th International Conference on Computer Design, 2011

Enhancing security via provably trustworthy hardware intellectual property.
Proceedings of the HOST 2011, 2011

2010
Hardware Trojans in Wireless Cryptographic ICs.
IEEE Design & Test of Computers, 2010

DFTT: Design for Trojan Test.
Proceedings of the 17th IEEE International Conference on Electronics, 2010

2009
Experiences in Hardware Trojan Design and Implementation.
Proceedings of the IEEE International Workshop on Hardware-Oriented Security and Trust, 2009

2008
Low complexity bit parallel multiplier for GF(2m) generated by equally-spaced trinomials.
Inf. Process. Lett., 2008

Hardware Trojan Detection Using Path Delay Fingerprint.
Proceedings of the IEEE International Workshop on Hardware-Oriented Security and Trust, 2008

2007
Dual-Residue Montgomery Multiplication.
Proceedings of the Network and Parallel Computing, IFIP International Conference, 2007

2006
Unbalanced Exponent Modular Reduction over Binary Field and Its Implementation.
Proceedings of the First International Conference on Innovative Computing, Information and Control (ICICIC 2006), 30 August, 2006

Interconnect Estimation for Mesh-Based Reconfigurable Computing.
Proceedings of the Embedded and Ubiquitous Computing, International Conference, 2006


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