Manil Dev Gomony
Orcid: 0000-0002-5889-0785
According to our database1,
Manil Dev Gomony authored at least 44 papers
between 2012 and 2026.
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Bibliography
2026
Proceedings of the 17th Workshop on Parallel Programming and Run-Time Management Techniques for Many-Core Architectures and 15th Workshop on Design Tools and Architectures for Multicore Embedded Computing Platforms, 2026
LOKI: a 0.266 pJ/SOP Digital SNN Accelerator with Multi-Cycle Clock-Gated SRAM in 22 nm.
Proceedings of the 31st Asia and South Pacific Design Automation Conference, 2026
2025
CoRR, November, 2025
DREAM-CIM: A Digital SRAM-Based CIM Accelerator for Energy- and Area-Efficient Edge AI.
IEEE Trans. Circuits Syst. Artif. Intell., September, 2025
LinkBo: An Adaptive Single-Wire, Low-Latency, and Fault-Tolerant Communications Interface for Variable-Distance Chip-to-Chip Systems.
CoRR, September, 2025
CoRR, May, 2025
CoRR, January, 2025
IACR Cryptol. ePrint Arch., 2025
LinkBo: A Single-Wire, Low-Latency, and Robust Protocol for Variable-Distance Chip-to-Chip Communications.
Proceedings of the 38th IEEE International System-on-Chip Conference, 2025
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2025
Proceedings of the IEEE European Test Symposium, 2025
Proceedings of the Design, Automation & Test in Europe Conference, 2025
CIMple: Standard-cell SRAM-based CIM with LUT-based split softmax for attention acceleration.
Proceedings of the 2025 Cross-Disciplinary Conference on Memory-Centric Computing (CCMCC), 2025
2024
Reconfigurable Signal Processing and DSP Hardware Generator for 5G and Beyond Transmitters.
IEEE Trans. Very Large Scale Integr. Syst., January, 2024
Hardware-aware training of models with synaptic delays for digital event-driven neuromorphic processors.
CoRR, 2024
A Scalable Hardware Architecture for Efficient Learning of Recurrent Neural Networks at the Edge.
Proceedings of the 32nd IFIP/IEEE International Conference on Very Large Scale Integration, 2024
Proceedings of the 32nd IFIP/IEEE International Conference on Very Large Scale Integration, 2024
Proceedings of the 32nd IFIP/IEEE International Conference on Very Large Scale Integration, 2024
LLRSymNet: A Low-Complex Neural Network for LLR Estimation Through Symmetry Exploitation.
Proceedings of the 2024 IEEE Global Communications Conference, 2024
Proceedings of the 27th Euromicro Conference on Digital System Design, 2024
Proceedings of the 61st ACM/IEEE Design Automation Conference, 2024
Run-time Non-uniform Quantization for Dynamic Neural Networks in Wireless Communication.
Proceedings of the 29th Asia and South Pacific Design Automation Conference, 2024
2023
Proceedings of the 41st IEEE International Conference on Computer Design, 2023
Proceedings of the IEEE European Test Symposium, 2023
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023
2022
IEEE Trans. Circuits Syst. I Regul. Pap., 2022
THOR - A Neuromorphic Processor with 7.29G TSOP$^2$/mm$^2$Js Energy-Throughput Efficiency.
CoRR, 2022
BrainTTA: A 35 fJ/op Compiler Programmable Mixed-Precision Transport-Triggered NN SoC.
CoRR, 2022
Proceedings of the 2022 Joint European Conference on Networks and Communications & 6G Summit, 2022
2021
Proceedings of the IEEE Workshop on Signal Processing Systems, 2021
2020
μ-Genie: A Framework for Memory-Aware Spatial Processor Architecture Co-Design Exploration.
Proceedings of the 23rd Euromicro Conference on Digital System Design, 2020
2019
Proceedings of the Analysis, Estimations, and Applications of Embedded Systems, 2019
Proceedings of the 22nd Euromicro Conference on Digital System Design, 2019
2018
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018
2017
IEEE Trans. Computers, 2017
2015
A Real-Time Multichannel Memory Controller and Optimal Mapping of Memory Clients to Memory Channels.
ACM Trans. Embed. Comput. Syst., 2015
A generic, scalable and globally arbitrated memory tree for shared DRAM access in real-time systems.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015
2014
Coupling TDM NoC and DRAM controller for cost and performance optimization of real-time systems.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014
2013
Virtual execution platforms for mixed-time-criticality systems: the CompSOC architecture and design flow.
SIGBED Rev., 2013
Architecture and optimal configuration of a real-time multi-channel memory controller.
Proceedings of the Design, Automation and Test in Europe, 2013
2012
Leveraging 802.11n frame aggregation to enhance QoS and power consumption in Wi-Fi networks.
Comput. Networks, 2012
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012