Karyofyllis Patsidis

According to our database, Karyofyllis Patsidis authored at least 4 papers between 2018 and 2022.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2022

IDLD: Instantaneous Detection of Leakage and Duplication of Identifiers used for Register Renaming.

Yiannakis Sazeides, Alex Gerber, Ron Gabor, Arkady Bramnik, George Papadimitriou, Dimitris Gizopoulos, Chrysostomos Nicopoulos, Giorgos Dimitrakopoulos, Karyofyllis Patsidis

Proceedings of the 55th IEEE/ACM International Symposium on Microarchitecture, 2022

2020

RISC-V2: A Scalable RISC-V Vector Processor.

Karyofyllis Patsidis, Chrysostomos Nicopoulos, Georgios Ch. Sirakoulis, Giorgos Dimitrakopoulos

Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

2019

Error-Shielded Register Renaming Sub-system for a Dynamically Scheduled Out-of-Order Core.

Ron Gabor, Yiannakis Sazeides, Arkady Bramnik, Alexandros Andreou, Chrysostomos Nicopoulos, Karyofyllis Patsidis, Dimitris Konstantinou, Giorgos Dimitrakopoulos

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

2018

A low-cost synthesizable RISC-V dual-issue processor core leveraging the compressed Instruction Set Extension.

Karyofyllis Patsidis, Dimitris Konstantinou, Chrysostomos Nicopoulos, Giorgos Dimitrakopoulos

Microprocess. Microsystems, 2018