Kaushik Gala

According to our database1, Kaushik Gala authored at least 11 papers between 2000 and 2003.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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PhD thesis 
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Links

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Bibliography

2003
Analysis and optimization of structured power/ground networks.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003

Fast on-chip inductance simulation using a precorrected-FFT method.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003

Table look-up based compact modeling for on-chip interconnect timing and noise analysis.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

Statistical delay computation considering spatial correlations.
Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003

2002
Inductance model and analysis methodology for high-speed on-chip interconnect.
IEEE Trans. Very Large Scale Integr. Syst., 2002

Worst case clock skew under power supply variations.
Proceedings of the 8th ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, 2002

A precorrected-FFT method for simulating on-chip inductance.
Proceedings of the 2002 IEEE/ACM International Conference on Computer-aided Design, 2002

2001
Inductance 101: Analysis and Design Issues.
Proceedings of the 38th Design Automation Conference, 2001

2000
Fast Analysis and Optimization of Power/Ground Networks.
Proceedings of the 2000 IEEE/ACM International Conference on Computer-Aided Design, 2000

On-chip inductance modeling.
Proceedings of the 10th ACM Great Lakes Symposium on VLSI 2000, 2000

On-chip inductance modeling and analysis.
Proceedings of the 37th Conference on Design Automation, 2000


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