Vladimir Zolotov

According to our database1, Vladimir Zolotov authored at least 80 papers between 2000 and 2021.

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Bibliography

2021
Project CodeNet: A Large-Scale AI for Code Dataset for Learning a Diversity of Coding Tasks.
CoRR, 2021

CodeNet: A Large-Scale AI for Code Dataset for Learning a Diversity of Coding Tasks.
Proceedings of the Neural Information Processing Systems Track on Datasets and Benchmarks 1, 2021

2019
Large Data Flow Graphs in Limited GPU Memory.
Proceedings of the 2019 IEEE International Conference on Big Data (IEEE BigData), 2019

2017
Analysis and Optimization of fastText Linear Text Classifier.
CoRR, 2017

2016
Sharing and Re-use of Statistical Timing Macro-Models across Multiple Voltage Domains.
Proceedings of the 29th International Conference on VLSI Design and 15th International Conference on Embedded Systems, 2016

Generation and use of statistical timing macro-models considering slew and load variability.
Proceedings of the 35th International Conference on Computer-Aided Design, 2016

Practical statistical static timing analysis with current source models.
Proceedings of the 53rd Annual Design Automation Conference, 2016

2015
Variation aware cross-talk aggressor alignment by mixed integer linear programming.
Proceedings of the 52nd Annual Design Automation Conference, 2015

2013
Order statistics for correlated random variables and its application to at-speed testing.
ACM Trans. Design Autom. Electr. Syst., 2013

2012
Testability-Driven Statistical Path Selection.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012

Path Criticality Computation in Parameterized Statistical Timing Analysis Using a Novel Operator.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012

Timing analysis with nonseparable statistical and deterministic variations.
Proceedings of the 49th Annual Design Automation Conference 2012, 2012

Reversible statistical <i>max/min</i> operation: concept and applications to timing.
Proceedings of the 49th Annual Design Automation Conference 2012, 2012

2011
Optimal statistical chip disposition.
Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011

Path criticality computation in parameterized statistical timing analysis.
Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011

2010
Statistical Path Selection for At-Speed Test.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

Transistor sizing of custom high-performance digital circuits with parametric yield considerations.
Proceedings of the 47th Design Automation Conference, 2010

2009
Optimal Test Margin Computation for At-Speed Structural Test.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009

Statistical Power Analysis for High-Performance Processors.
J. Low Power Electron., 2009

Voltage binning under process variation.
Proceedings of the 2009 International Conference on Computer-Aided Design, 2009

Pre-ATPG path selection for near optimal post-ATPG process space coverage.
Proceedings of the 2009 International Conference on Computer-Aided Design, 2009

Statistical ordering of correlated timing quantities and its application for path ranking.
Proceedings of the 46th Design Automation Conference, 2009

Statistical multilayer process space coverage for at-speed test.
Proceedings of the 46th Design Automation Conference, 2009

2008
Coupling Noise.
Proceedings of the Handbook of Algorithms for Physical Design Automation., 2008

Statistical Modeling and Analysis of Static Leakage and Dynamic Switching Power.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2008

Optimal Margin Computation for At-Speed Test.
Proceedings of the Design, Automation and Test in Europe, 2008

Incremental Criticality and Yield Gradients.
Proceedings of the Design, Automation and Test in Europe, 2008

Static timing: Back to our roots.
Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008

2007
Robust Extraction of Spatial Correlation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

Compact modeling of variational waveforms.
Proceedings of the 2007 International Conference on Computer-Aided Design, 2007

Variation-aware performance verification using at-speed structural test and statistical timing.
Proceedings of the 2007 International Conference on Computer-Aided Design, 2007

2006
Optimal placement of power-supply pads and pins.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

Impact of stress-induced backflow on full-chip electromigration risk assessment.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

Criticality computation in parameterized statistical timing.
Proceedings of the 43rd Design Automation Conference, 2006

2005
Discrete Vt assignment and gate sizing using a self-snapping continuous formulation.
Proceedings of the 2005 International Conference on Computer-Aided Design, 2005

Accurate delay computation for noisy waveform shapes.
Proceedings of the 2005 International Conference on Computer-Aided Design, 2005

Gate sizing using incremental parameterized statistical timing analysis.
Proceedings of the 2005 International Conference on Computer-Aided Design, 2005

Pessimism reduction in crosstalk noise aware STA.
Proceedings of the 2005 International Conference on Computer-Aided Design, 2005

Optimization objectives and models of variation for statistical gate sizing.
Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, 2005

Parameterized block-based statistical timing analysis with non-gaussian parameters, nonlinear delay functions.
Proceedings of the 42nd Design Automation Conference, 2005

Circuit optimization using statistical static timing analysis.
Proceedings of the 42nd Design Automation Conference, 2005

2004
Postroute gate sizing for crosstalk noise reduction.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004

Statistical clock skew analysis considering intradie-process variations.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004

A Methodology for Chip-Level Electromigration Risk Assessment and Product Qualification.
Proceedings of the 5th International Symposium on Quality of Electronic Design (ISQED 2004), 2004

Delay noise pessimism reduction by logic correlations.
Proceedings of the 2004 International Conference on Computer-Aided Design, 2004

False-Noise Analysis for Domino Circuits.
Proceedings of the 2004 Design, 2004

A stochastic approach To power grid analysis.
Proceedings of the 41th Design Automation Conference, 2004

Static timing analysis using backward signal propagation.
Proceedings of the 41th Design Automation Conference, 2004

2003
Fast on-chip inductance simulation using a precorrected-FFT method.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003

Static electromigration analysis for on-chip signal interconnects.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003

Statistical timing analysis using bounds and selective enumeration.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003

Static Electromigration Analysis for Signal Interconnects.
Proceedings of the 4th International Symposium on Quality of Electronic Design (ISQED 2003), 2003

Post-Route Gate Sizing for Crosstalk Noise Reduction.
Proceedings of the 4th International Symposium on Quality of Electronic Design (ISQED 2003), 2003

Table look-up based compact modeling for on-chip interconnect timing and noise analysis.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

Vectorless Analysis of Supply Noise Induced Delay Variation.
Proceedings of the 2003 International Conference on Computer-Aided Design, 2003

SOI Transistor Model for Fast Transient Simulation.
Proceedings of the 2003 International Conference on Computer-Aided Design, 2003

Statistical Clock Skew Analysis Considering Intra-Die Process Variations.
Proceedings of the 2003 International Conference on Computer-Aided Design, 2003

Statistical Timing Analysis for Intra-Die Process Variations with Spatial Correlations.
Proceedings of the 2003 International Conference on Computer-Aided Design, 2003

Statistical Timing Analysis Using Bounds.
Proceedings of the 2003 Design, 2003

Computation and Refinement of Statistical Bounds on Circuit Delay.
Proceedings of the 40th Design Automation Conference, 2003

Statistical delay computation considering spatial correlations.
Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003

2002
Inductance model and analysis methodology for high-speed on-chip interconnect.
IEEE Trans. Very Large Scale Integr. Syst., 2002

False-noise analysis using logic implications.
ACM Trans. Design Autom. Electr. Syst., 2002

Slope propagation in static timing analysis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002

Worst case clock skew under power supply variations.
Proceedings of the 8th ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, 2002

Statistical timing analysis using bounds and selective enumeration.
Proceedings of the 8th ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, 2002

Noise Injection and Propagation in High Performance Designs.
Proceedings of the 3rd International Symposium on Quality of Electronic Design, 2002

False-Noise Analysis Using Resolution Method.
Proceedings of the 3rd International Symposium on Quality of Electronic Design, 2002

Noise propagation and failure criteria for VLSI designs.
Proceedings of the 2002 IEEE/ACM International Conference on Computer-aided Design, 2002

A precorrected-FFT method for simulating on-chip inductance.
Proceedings of the 2002 IEEE/ACM International Conference on Computer-aided Design, 2002

Analysis of Noise Avoidance Techniques in DSM Interconnects Using a Complete Crosstalk Noise Model .
Proceedings of the 2002 Design, 2002

2001
A Global Driver Sizing Tool for Functional Crosstalk Noise Avoidance.
Proceedings of the 2nd International Symposium on Quality of Electronic Design (ISQED 2001), 2001

False-Noise Analysis using Logic Implications.
Proceedings of the 2001 IEEE/ACM International Conference on Computer-Aided Design, 2001

Driver Modeling and Alignment for Worst-Case Delay Noise.
Proceedings of the 38th Design Automation Conference, 2001

Inductance 101: Analysis and Design Issues.
Proceedings of the 38th Design Automation Conference, 2001

2000
Model and analysis for combined package and on-chip power grid simulation.
Proceedings of the 2000 International Symposium on Low Power Electronics and Design, 2000

Slope Propagation in Static Timing Analysis.
Proceedings of the 2000 IEEE/ACM International Conference on Computer-Aided Design, 2000

On-chip inductance modeling.
Proceedings of the 10th ACM Great Lakes Symposium on VLSI 2000, 2000

ClariNet: a noise analysis tool for deep submicron design.
Proceedings of the 37th Conference on Design Automation, 2000

On-chip inductance modeling and analysis.
Proceedings of the 37th Conference on Design Automation, 2000


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