Savithri Sundareswaran

According to our database1, Savithri Sundareswaran authored at least 24 papers between 1999 and 2019.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2019
SLECTS: Slew-Driven Clock Tree Synthesis.
IEEE Trans. Very Large Scale Integr. Syst., 2019

2015
Decoupling Capacitance Design Strategies for Power Delivery Networks with Power Gating.
ACM Trans. Design Autom. Electr. Syst., 2015

2011
A sensitivity-aware methodology to improve cell layouts for DFM guidelines.
Proceedings of the 12th International Symposium on Quality Electronic Design, 2011

2010
Total sensitivity based dfm optimization of standard library cells.
Proceedings of the 2010 International Symposium on Physical Design, 2010

2009
Characterization of sequential cells for constraint sensitivities.
Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009

2008
A timing methodology considering within-die clock skew variations.
Proceedings of the 21st Annual IEEE International SoC Conference, SoCC 2008, 2008

Characterization of Standard Cells for Intra-Cell Mismatch Variations.
Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008

Transistor-Specific Delay Modeling for SSTA.
Proceedings of the Design, Automation and Test in Europe, 2008

Faster statistical cell characterization using adjoint sensitivity analysis.
Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008

2007
Analyzing the risk of timing modeling based on path delay tests.
Proceedings of the 2007 IEEE International Test Conference, 2007

Small-Delay Defect Detection in the Presence of Process Variations.
Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007

A novel technique for incremental analysis of on-chip power distribution networks.
Proceedings of the 2007 International Conference on Computer-Aided Design, 2007

On-Chip Decoupling Capacitance and P/G Wire Co-optimization for Dynamic Noise.
Proceedings of the 44th Design Automation Conference, 2007

2006
Optimal placement of power-supply pads and pins.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

A fast on-chip decoupling capacitance budgeting algorithm using macromodeling and linear programming.
Proceedings of the 43rd Design Automation Conference, 2006

2004
A stochastic approach To power grid analysis.
Proceedings of the 41th Design Automation Conference, 2004

2003
Impact of Low-Impedance Substrate on Power Supply Integrity.
IEEE Des. Test Comput., 2003

Vectorless Analysis of Supply Noise Induced Delay Variation.
Proceedings of the 2003 International Conference on Computer-Aided Design, 2003

Statistical delay computation considering spatial correlations.
Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003

2002
Slope propagation in static timing analysis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002

2001
On the interaction of power distribution network with substrate.
Proceedings of the 2001 International Symposium on Low Power Electronics and Design, 2001

2000
An Assertion Based Technique for Transistor Level Dynamic Power Estimation.
Proceedings of the 13th International Conference on VLSI Design (VLSI Design 2000), 2000

Slope Propagation in Static Timing Analysis.
Proceedings of the 2000 IEEE/ACM International Conference on Computer-Aided Design, 2000

1999
A Three-Tier Assertion Technique for Spice Verification of Transistor Level Timing Analysis.
Proceedings of the 12th International Conference on VLSI Design (VLSI Design 1999), 1999


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