Savithri Sundareswaran

According to our database, Savithri Sundareswaran authored at least 24 papers between 1999 and 2019.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2019

SLECTS: Slew-Driven Clock Tree Synthesis.

Weicheng Liu, Can Sitik, Emre Salman, Baris Taskin, Savithri Sundareswaran, Benjamin Huang

IEEE Trans. Very Large Scale Integr. Syst., 2019

2015

Decoupling Capacitance Design Strategies for Power Delivery Networks with Power Gating.

Tong Xu, Peng Li, Savithri Sundareswaran

ACM Trans. Design Autom. Electr. Syst., 2015

2011

A sensitivity-aware methodology to improve cell layouts for DFM guidelines.

Savithri Sundareswaran, Robert L. Maziasz, Vladimir Rozenfeld, Mikhail Sotnikov, Mukhanov Konstantin

Proceedings of the 12th International Symposium on Quality Electronic Design, 2011

2010

Total sensitivity based dfm optimization of standard library cells.

Yongchan Ban, Savithri Sundareswaran, David Z. Pan

Proceedings of the 2010 International Symposium on Physical Design, 2010

2009

Characterization of sequential cells for constraint sensitivities.

Savithri Sundareswaran, Rajendran Panda, Jacob A. Abraham, Yun Zhang, Amit Mittal

Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009

2008

A timing methodology considering within-die clock skew variations.

Savithri Sundareswaran, Lucie Nechanicka, Rajendran Panda, Sergey Gavrilov, Roman A. Solovyev, Jacob A. Abraham

Proceedings of the 21st Annual IEEE International SoC Conference, SoCC 2008, 2008

Characterization of Standard Cells for Intra-Cell Mismatch Variations.

Savithri Sundareswaran, Jacob A. Abraham, Alexandre Ardelea, Rajendran Panda

Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008

Transistor-Specific Delay Modeling for SSTA.

Brian Cline, Kaviraj Chopra, David T. Blaauw, Andres Torres, Savithri Sundareswaran

Proceedings of the Design, Automation and Test in Europe, 2008

Faster statistical cell characterization using adjoint sensitivity analysis.

Ben Gu, Kiran K. Gullapalli, Yun Zhang, Savithri Sundareswaran

Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008

2007

Analyzing the risk of timing modeling based on path delay tests.

Pouria Bastani, Benjamin N. Lee, Li-C. Wang, Savithri Sundareswaran, Magdy S. Abadir

Proceedings of the 2007 IEEE International Test Conference, 2007

Small-Delay Defect Detection in the Presence of Process Variations.

Rajeshwary Tayade, Savithri Sundareswaran, Jacob A. Abraham

Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007

A novel technique for incremental analysis of on-chip power distribution networks.

Yuhong Fu, Rajendran Panda, Ben Reschke, Savithri Sundareswaran, Min Zhao

Proceedings of the 2007 International Conference on Computer-Aided Design, 2007

On-Chip Decoupling Capacitance and P/G Wire Co-optimization for Dynamic Noise.

Min Zhao, Rajendran Panda, Ben Reschke, Yuhong Fu, Trudi Mewett, Sri Chandrasekaran, Savithri Sundareswaran, Shu Yan

Proceedings of the 44th Design Automation Conference, 2007

2006

Optimal placement of power-supply pads and pins.

Min Zhao, Yuhong Fu, Vladimir Zolotov, Savithri Sundareswaran, Rajendran Panda

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

A fast on-chip decoupling capacitance budgeting algorithm using macromodeling and linear programming.

Min Zhao, Rajendran Panda, Savithri Sundareswaran, Shu Yan, Yuhong Fu

Proceedings of the 43rd Design Automation Conference, 2006

2004

A stochastic approach To power grid analysis.

Sanjay Pant, David T. Blaauw, Vladimir Zolotov, Savithri Sundareswaran, Rajendran Panda

Proceedings of the 41th Design Automation Conference, 2004

2003

Impact of Low-Impedance Substrate on Power Supply Integrity.

Rajendran Panda, Savithri Sundareswaran, David T. Blaauw

IEEE Des. Test Comput., 2003

Vectorless Analysis of Supply Noise Induced Delay Variation.

Sanjay Pant, David T. Blaauw, Vladimir Zolotov, Savithri Sundareswaran, Rajendran Panda

Proceedings of the 2003 International Conference on Computer-Aided Design, 2003

Statistical delay computation considering spatial correlations.

Aseem Agarwal, David T. Blaauw, Vladimir Zolotov, Savithri Sundareswaran, Min Zhao, Kaushik Gala, Rajendran Panda

Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003

2002

Slope propagation in static timing analysis.

David T. Blaauw, Vladimir Zolotov, Savithri Sundareswaran

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002

2001

On the interaction of power distribution network with substrate.

Rajendran Panda, Savithri Sundareswaran, David T. Blaauw

Proceedings of the 2001 International Symposium on Low Power Electronics and Design, 2001

2000

An Assertion Based Technique for Transistor Level Dynamic Power Estimation.

Savithri Sundareswaran, R. Venkatesan, S. Bhaskar

Proceedings of the 13th International Conference on VLSI Design (VLSI Design 2000), 2000

Slope Propagation in Static Timing Analysis.

David T. Blaauw, Vladimir Zolotov, Savithri Sundareswaran, Chanhee Oh, Rajendran Panda

Proceedings of the 2000 IEEE/ACM International Conference on Computer-Aided Design, 2000

1999

A Three-Tier Assertion Technique for Spice Verification of Transistor Level Timing Analysis.

Savithri Sundareswaran, David T. Blaauw, Abhijit Dharchoudhury

Proceedings of the 12th International Conference on VLSI Design (VLSI Design 1999), 1999