Rajendran Panda

Int. J. Parallel Program., 2010

2009

<i>A Special Issue on the</i> "22nd IEEE International Conference on VLSI Design" New Delhi, India, 5-9 January 2009.

[BibT_eX]

[DOI]

Preeti Ranjan Panda

J. Low Power Electron., 2009

Characterization of sequential cells for constraint sensitivities.

[BibT_eX]

[DOI]

Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009

2008

Coupling Noise.

[BibT_eX]

[DOI]

Murat R. Becer

Proceedings of the Handbook of Algorithms for Physical Design Automation., 2008

A timing methodology considering within-die clock skew variations.

[BibT_eX]

[DOI]

Proceedings of the 21st Annual IEEE International SoC Conference, SoCC 2008, 2008

Accelerating Clock Mesh Simulation Using Matrix-Level Macromodels and Dynamic Time Step Rounding.

[BibT_eX]

[DOI]

Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008

Characterization of Standard Cells for Intra-Cell Mismatch Variations.

[BibT_eX]

[DOI]

Jacob A. Abraham

Alexandre Ardelea

Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008

2007

Analysis of large clock meshes via harmonic-weighted model order reduction and port sliding.

[BibT_eX]

[DOI]

Proceedings of the 2007 International Conference on Computer-Aided Design, 2007

A novel technique for incremental analysis of on-chip power distribution networks.

[BibT_eX]

[DOI]

Yuhong Fu

Ben Reschke

Proceedings of the 2007 International Conference on Computer-Aided Design, 2007

On-Chip Decoupling Capacitance and P/G Wire Co-optimization for Dynamic Noise.

[BibT_eX]

[DOI]

Shu Yan

Proceedings of the 44th Design Automation Conference, 2007

2006

Optimal placement of power-supply pads and pins.

[BibT_eX]

[DOI]

Yuhong Fu

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

Impact of stress-induced backflow on full-chip electromigration risk assessment.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

A fast on-chip decoupling capacitance budgeting algorithm using macromodeling and linear programming.

[BibT_eX]

[DOI]

Shu Yan

Yuhong Fu

Proceedings of the 43rd Design Automation Conference, 2006

Stochastic variational analysis of large power grids considering intra-die correlations.

[BibT_eX]

[DOI]

Proceedings of the 43rd Design Automation Conference, 2006

2005

Pessimism reduction in crosstalk noise aware STA.

[BibT_eX]

[DOI]

Proceedings of the 2005 International Conference on Computer-Aided Design, 2005

Stochastic Power Grid Analysis Considering Process Variations.

[BibT_eX]

[DOI]

Proceedings of the 2005 Design, 2005

2004

Crosstalk noise control in an SoC physical design flow.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004

Postroute gate sizing for crosstalk noise reduction.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004

A Methodology for Chip-Level Electromigration Risk Assessment and Product Qualification.

[BibT_eX]

[DOI]

Proceedings of the 5th International Symposium on Quality of Electronic Design (ISQED 2004), 2004

Delay noise pessimism reduction by logic correlations.

[BibT_eX]

[DOI]

Proceedings of the 2004 International Conference on Computer-Aided Design, 2004

False-Noise Analysis for Domino Circuits.

[BibT_eX]

[DOI]

Proceedings of the 2004 Design, 2004

A stochastic approach To power grid analysis.

[BibT_eX]

[DOI]

Sanjay Pant

Proceedings of the 41th Design Automation Conference, 2004

2003

Fast on-chip inductance simulation using a precorrected-FFT method.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003

Early probabilistic noise estimation for capacitively coupled interconnects.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003

Impact of Low-Impedance Substrate on Power Supply Integrity.

[BibT_eX]

[DOI]

IEEE Des. Test Comput., 2003

Static Electromigration Analysis for Signal Interconnects.

[BibT_eX]

[DOI]

Proceedings of the 4th International Symposium on Quality of Electronic Design (ISQED 2003), 2003

Post-Route Gate Sizing for Crosstalk Noise Reduction.

[BibT_eX]

[DOI]

Proceedings of the 4th International Symposium on Quality of Electronic Design (ISQED 2003), 2003

Signal integrity management in an SoC physical design flow.

[BibT_eX]

[DOI]

Proceedings of the 2003 International Symposium on Physical Design, 2003

Table look-up based compact modeling for on-chip interconnect timing and noise analysis.

[BibT_eX]

[DOI]

Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

Vectorless Analysis of Supply Noise Induced Delay Variation.

[BibT_eX]

[DOI]

Sanjay Pant

Proceedings of the 2003 International Conference on Computer-Aided Design, 2003

SOI Transistor Model for Fast Transient Simulation.

[BibT_eX]

[DOI]

Proceedings of the 2003 International Conference on Computer-Aided Design, 2003

Statistical delay computation considering spatial correlations.

[BibT_eX]

[DOI]

Aseem Agarwal

Kaushik Gala

Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003

2002

Duet: an accurate leakage estimation and optimization tool for dual-V<sub>t</sub> circuits.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2002

Hierarchical analysis of power distribution networks.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002

Worst case clock skew under power supply variations.

[BibT_eX]

[DOI]

Proceedings of the 8th ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, 2002

Noise Injection and Propagation in High Performance Designs.

[BibT_eX]

[DOI]

Proceedings of the 3rd International Symposium on Quality of Electronic Design, 2002

False-Noise Analysis Using Resolution Method.

[BibT_eX]

[DOI]

Proceedings of the 3rd International Symposium on Quality of Electronic Design, 2002

Pre-route Noise Estimation in Deep Submicron Integrated Circuits.

[BibT_eX]

[DOI]

Proceedings of the 3rd International Symposium on Quality of Electronic Design, 2002

Noise propagation and failure criteria for VLSI designs.

[BibT_eX]

[DOI]

Proceedings of the 2002 IEEE/ACM International Conference on Computer-aided Design, 2002

A precorrected-FFT method for simulating on-chip inductance.

[BibT_eX]

[DOI]

Proceedings of the 2002 IEEE/ACM International Conference on Computer-aided Design, 2002

Analysis of Noise Avoidance Techniques in DSM Interconnects Using a Complete Crosstalk Noise Model .

[BibT_eX]

[DOI]

Proceedings of the 2002 Design, 2002

2001

On the interaction of power distribution network with substrate.

[BibT_eX]

[DOI]

Proceedings of the 2001 International Symposium on Low Power Electronics and Design, 2001

2000

Design and Analysis of Power Distribution Networks with Accurate RLC Models.

[BibT_eX]

[DOI]

Proceedings of the 13th International Conference on VLSI Design (VLSI Design 2000), 2000

Model and analysis for combined package and on-chip power grid simulation.

[BibT_eX]

[DOI]

Proceedings of the 2000 International Symposium on Low Power Electronics and Design, 2000

Slope Propagation in Static Timing Analysis.

[BibT_eX]

[DOI]

Chanhee Oh

Proceedings of the 2000 IEEE/ACM International Conference on Computer-Aided Design, 2000

On-chip inductance modeling.

[BibT_eX]

[DOI]

Proceedings of the 10th ACM Great Lakes Symposium on VLSI 2000, 2000

Hierarchical analysis of power distribution networks.

[BibT_eX]

[DOI]

Proceedings of the 37th Conference on Design Automation, 2000

On-chip inductance modeling and analysis.

[BibT_eX]

[DOI]

Proceedings of the 37th Conference on Design Automation, 2000

Current signature compression for IR-drop analysis.

[BibT_eX]

[DOI]

Proceedings of the 37th Conference on Design Automation, 2000

Removing user specified false paths from timing graphs.

[BibT_eX]

[DOI]

Abhijit Das

Proceedings of the 37th Conference on Design Automation, 2000

1999

Stand-by Power Minimization Through Simultaneous Threshold Voltage Selection and Circuit Sizing.

[BibT_eX]

[DOI]

Tim Edwards

Chanhee Oh

Jingyan Zuo

Proceedings of the 36th Conference on Design Automation, 1999

1998

Post-Mapping Transformations for Low-Power Synthesis.

[BibT_eX]

[DOI]

Farid N. Najm

VLSI Design, 1998

Emerging power management tools for processor design.

[BibT_eX]

[DOI]

Chanhee Oh

Tim Edwards

Proceedings of the 1998 International Symposium on Low Power Electronics and Design, 1998

CMOS Combinational Circuit Sizing by Stage-wise Tapering.

[BibT_eX]

[DOI]

Satyamurthy Pullela

Gopal Vija

Proceedings of the 1998 Design, 1998

Migration: A New Technique to Improve Synthesized Designs Through Incremental Customization.

[BibT_eX]

[DOI]

Tim Edwards

Joe Norton

Proceedings of the 35th Conference on Design Automation, 1998

Design and Analysis of Power Distribution Networks in PowerPC Microprocessors.

[BibT_eX]

[DOI]

Proceedings of the 35th Conference on Design Automation, 1998

1997

Library-less synthesis for static CMOS combinational logic circuits.

[BibT_eX]

[DOI]

Gopalakrishnan Vijayan

Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, 1997

Technology-Dependent Transformations for Low-Power Synthesis.

[BibT_eX]

[DOI]