Kazuya Tanigawa

According to our database, Kazuya Tanigawa authored at least 11 papers between 2002 and 2015.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2015

Development of a Trax Artificial Intelligence algorithm using path and edge.

Ryo Okuda, Tomohiro Tanaka, Keisuke Yamamoto, Takumu Yahagi, Kazuya Tanigawa

Proceedings of the 2015 International Conference on Field Programmable Technology, 2015

2012

A Physical Design Method for a New Memory-Based Reconfigurable Architecture without Switch Blocks.

Masatoshi Nakamura, Masato Inagi, Kazuya Tanigawa, Tetsuo Hironaka, Masayuki Sato, Takashi Ishiguro

IEICE Trans. Inf. Syst., 2012

2011

EDA Environment for Evaluating a New Switch-Block-Free Reconfigurable Architecture.

Masatoshi Nakamura, Masato Inagi, Kazuya Tanigawa, Tetsuo Hironaka, Masayuki Sato, Takashi Ishiguro

Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs, 2011

Design consideration for reconfigurable processor DS-HIE - Trade-off between performance and chip area.

Kazuya Tanigawa, Tetsuo Hironaka

Proceedings of the International SoC Design Conference, 2011

2010

Comparison of Bit Serial Computation with Bit Parallel Computation for Reconfigurable Processor.

Kazuya Tanigawa, Ken'ichi Umeda, Tetsuo Hironaka

Proceedings of the Reconfigurable Computing: Architectures, 2010

2008

Evaluation of compact high-throughput reconfigurable architecture based on bit-serial computation.

Kazuya Tanigawa, Tetsuo Hironaka

Proceedings of the 2008 International Conference on Field-Programmable Technology, 2008

Exploring compact design on high throughput coarse grained reconfigurable architectures.

Kazuya Tanigawa, Tetsuya Zuyama, Takuro Uchida, Tetsuo Hironaka

Proceedings of the FPL 2008, 2008

2006

Unified Data/Instruction Cache with Hierarchical Multi-Port Architecture and Hidden Precharge Pipeline.

Koh Johguchi, Zhaomin Zhu, Hans Jürgen Mattausch, Tetsushi Koide, Tetsuo Hironaka, Kazuya Tanigawa

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006

2005

Design of superscalar processor with multi-bank register file.

Tadashi Saito, Moto Maeda, Tetsuo Hironaka, Kazuya Tanigawa, Tetsuya Sueyoshi, Ken-ichi Aoyama, Tetsushi Koide, Hans Jürgen Mattausch

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

2003

A coarse-grained reconfigurable architecture with low cost configuration data compression mechanism.

Kazuya Tanigawa, Takashi Kawasaki, Tetsuo Hironaka

Proceedings of the 2003 IEEE International Conference on Field-Programmable Technology, 2003

2002

A Generalized Execution Model for Programming on Reconfigurable Architectures and an Architecture Supporting the Model.

Kazuya Tanigawa, Tetsuo Hironaka, Akira Kojima, Noriyoshi Yoshida

Proceedings of the Field-Programmable Logic and Applications, 2002