Masato Inagi

According to our database, Masato Inagi authored at least 20 papers between 2002 and 2023.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2023

Feature Vectors Based on Wire Width and Distance for Lithography Hotspot Detection.

Gaku Kataoka, Masahiro Yamamoto, Masato Inagi, Shinobu Nagayama, Shin'ichi Wakabayashi

IPSJ Trans. Syst. LSI Des. Methodol., 2023

2018

A Nearest Neighbor Search Engine Using Distance-Based Hashing.

Toshitaka Ito, Yuri Itotani, Shin'ichi Wakabayashi, Shinobu Nagayama, Masato Inagi

Proceedings of the International Conference on Field-Programmable Technology, 2018

Novel Feature Vectors Considering Distances between Wires for Lithography Hotspot Detection.

Gaku Kataoka, Masato Inagi, Shinobu Nagayama, Shin'ichi Wakabayashi

Proceedings of the 21st Euromicro Conference on Digital System Design, 2018

An Approximate Nearest Neighbor Search Algorithm Using Distance-Based Hashing.

Yuri Itotani, Shin'ichi Wakabayashi, Shinobu Nagayama, Masato Inagi

Proceedings of the Database and Expert Systems Applications, 2018

2016

An efficient FPGA implementation of Mahalanobis distance-based outlier detection for streaming data.

Yuto Arai, Shin'ichi Wakabayashi, Shinobu Nagayama, Masato Inagi

Proceedings of the 2016 International Conference on Field-Programmable Technology, 2016

2015

Inter-FPGA Routing for Partially Time-Multiplexing Inter-FPGA Signals on Multi-FPGA Systems with Various Topologies.

Masato Inagi, Yuichi Nakamura, Yasuhiro Takashima, Shin'ichi Wakabayashi

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2015

2014

An Area Efficient Regular Expression Matching Engine Using Partial Reconfiguration for Quick Pattern Updating.

Yoichi Wakaba, Shin'ichi Wakabayashi, Shinobu Nagayama, Masato Inagi

IPSJ Trans. Syst. LSI Des. Methodol., 2014

An ILP-Based Optimal Circuit Mapping Method for PLDs.

Hiroki Nishiyama, Masato Inagi, Shin'ichi Wakabayashi, Shinobu Nagayama, Keisuke Inoue, Mineo Kaneko

Proceedings of the 2014 IEEE International Parallel & Distributed Processing Symposium Workshops, 2014

2013

A Flexible and Compact Regular Expression Matching Engine Using Partial Reconfiguration for FPGA.

Yoichi Wakaba, Shinobu Nagayama, Shin'ichi Wakabayashi, Masato Inagi

Proceedings of the 2013 Euromicro Conference on Digital System Design, 2013

A Multithreaded Parallel Global Routing Method with Overlapped Routing Regions.

Yasuhiro Shintani, Masato Inagi, Shinobu Nagayama, Shin'ichi Wakabayashi

Proceedings of the 2013 Euromicro Conference on Digital System Design, 2013

2012

A Physical Design Method for a New Memory-Based Reconfigurable Architecture without Switch Blocks.

Masatoshi Nakamura, Masato Inagi, Kazuya Tanigawa, Tetsuo Hironaka, Masayuki Sato, Takashi Ishiguro

IEICE Trans. Inf. Syst., 2012

2011

EDA Environment for Evaluating a New Switch-Block-Free Reconfigurable Architecture.

Masatoshi Nakamura, Masato Inagi, Kazuya Tanigawa, Tetsuo Hironaka, Masayuki Sato, Takashi Ishiguro

Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs, 2011

An Efficient Hardware Matching Engine for Regular Expression with Nested Kleene Operators.

Yoichi Wakaba, Masato Inagi, Shin'ichi Wakabayashi, Shinobu Nagayama

Proceedings of the International Conference on Field Programmable Logic and Applications, 2011

2010

Globally Optimal Time-multiplexing of Inter-FPGA Connections for Multi-FPGA Prototyping Systems.

Masato Inagi, Yasuhiro Takashima, Yuichi Nakamura

IPSJ Trans. Syst. LSI Des. Methodol., 2010

2009

Globally optimal time-multiplexing in inter-FPGA connections for accelerating multi-FPGA systems.

Masato Inagi, Yasuhiro Takashima, Yuichi Nakamura

Proceedings of the 19th International Conference on Field Programmable Logic and Applications, 2009

2008

Optimal Time-Multiplexing in Inter-FPGA Connections for Accelerating Multi-FPGA Prototyping Systems.

Masato Inagi, Yasuhiro Takashima, Yuichi Nakamura, Atsushi Takahashi

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008

ILP-based optimization of time-multiplexed I/O assignment for multi-FPGA systems.

Masato Inagi, Yasuhiro Takashima, Yuichi Nakamura, Atsushi Takahashi

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

2007

A Performance-Driven Circuit Bipartitioning Method Considering Time-Multiplexed I/Os.

Masato Inagi, Yasuhiro Takashima, Yuichi Nakamura, Yoji Kajitani

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2007

2006

A performance-driven circuit bipartitioning algorithm for multi-FPGA implementation with time-multiplexed I/Os.

Masato Inagi, Yasuhiro Takashima, Yuichi Nakamura, Yoji Kajitani

Proceedings of the 2006 IEEE International Conference on Field Programmable Technology, 2006

2002

An Improvement of Network-Flow Based Multi-Way Circuit Partitioning Algorithm.

Kengo R. Azegami, Masato Inagi, Atsushi Takahashi, Yoji Kajitani

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2002