Ke-Chung Wu

According to our database, Ke-Chung Wu authored at least 6 papers between 2009 and 2025.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2025

7.1 A 212.5Gb/s DSP-Based PAM-4 Transceiver with 50dB Loss Compensation for Large AI System Interconnects in 4nm FinFET.

Ehung Chen, Henry Park, Mohammed Abdullatif, Miguel Gandara, Ahmed ElShater, Amr Khashaba, Shih-Hao Huang, Tsz-Bin Liu, Atharav Atharav, Joonyeong Lee, Qaiser Nehal, Mohamed Megahed, Yusang Chun, Cheng-En Shieh, Vidhan Jolly, SoonWon Kwon, Hsin-Ta Chien, Ke-Chung Wu, Cheng-En Liu, Peng Yan, Po-Jui Li, Chun-Han Chen, Tzu-Shun Lin, Pei-Chieh Liu, Tamer A. Ali

Proceedings of the IEEE International Solid-State Circuits Conference, 2025

2019

A 180mW 56Gb/s DSP-Based Transceiver for High Density IOs in Data Center Switches in 7nm FinFET Technology.

Tamer A. Ali, Ramy Yousry, Henry Park, Ehung Chen, Po-Shuan Weng, Yi-Chieh Huang, Chun-Cheng Liu, Chien-Hua Wu, Shih-Hao Huang, Chungshi Lin, Ke-Chung Wu, Kun-Hung Tsai, Kai-Wen Tan, Ahmed ElShater, Kuang-Ren Chen, Wei-Hao Tsai, Huan-Sheng Chen, Weiyu Leng, Mazen Soliman

Proceedings of the IEEE International Solid- State Circuits Conference, 2019

2010

A 2 , ˟, 25-Gb/s Receiver With 2: 5 DMUX for 100-Gb/s Ethernet.

Ke-Chung Wu, Jri Lee

IEEE J. Solid State Circuits, 2010

A 2×25Gb/s deserializer with 2∶5 DMUX for 100Gb/s ethernet applications.

Ke-Chung Wu, Jri Lee

Proceedings of the IEEE International Solid-State Circuits Conference, 2010

2009

A 20-Gb/s Full-Rate Linear Clock and Data Recovery Circuit With Automatic Frequency Acquisition.

Jri Lee, Ke-Chung Wu

IEEE J. Solid State Circuits, 2009

A 20Gb/s full-rate linear CDR circuit with automatic frequency acquisition.

Jri Lee, Ke-Chung Wu

Proceedings of the IEEE International Solid-State Circuits Conference, 2009