Keewon Cho

Orcid: 0000-0003-0641-774X

Affiliations:

Yonsei University, Seoul, South Korea

According to our database¹, Keewon Cho authored at least 14 papers between 2013 and 2022.

Collaborative distances:

Dijkstra number² of four.
Erdős number³ of four.

Timeline

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PhD thesis

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Bibliography

2022

A 1ynm 1.25V 8Gb, 16Gb/s/pin GDDR6-based Accelerator-in-Memory supporting 1TFLOPS MAC Operation and Various Activation Functions for Deep-Learning Applications.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Solid-State Circuits Conference, 2022

2020

Fail Memory Configuration Set for RA Estimation.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Test Conference, 2020

2019

An Efficient BIRA Utilizing Characteristics of Spare Pivot Faults.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

2018

Fast Built-In Redundancy Analysis Based on Sequential Spare Line Allocation.

[BibT_eX]

[DOI]

IEEE Trans. Reliab., 2018

Fault Group Pattern Matching With Efficient Early Termination for High-Speed Redundancy Analysis.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

A Statistic-Based Scan Chain Reordering for Energy-Quality Scalable Scan Test.

[BibT_eX]

[DOI]

IEEE J. Emerg. Sel. Topics Circuits Syst., 2018

2-D Failure Bitmap Compression Using Line Fault Marking Method.

[BibT_eX]

[DOI]

Proceedings of the International SoC Design Conference, 2018

2017

Hardware-Efficient Built-In Redundancy Analysis for Memory With Various Spares.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2017

An efficient built-in self-repair scheme for area reduction.

[BibT_eX]

[DOI]

Proceedings of the International SoC Design Conference, 2017

2016

A Survey of Repair Analysis Algorithms for Memories.

[BibT_eX]

[DOI]

ACM Comput. Surv., 2016

Discussion of cost-effective redundancy architectures.

[BibT_eX]

[DOI]

Proceedings of the International SoC Design Conference, 2016

2015

Near optimal repair rate built-in redundancy analysis with very small hardware overhead.

[BibT_eX]

[DOI]

Proceedings of the Sixteenth International Symposium on Quality Electronic Design, 2015

2014

A Delay Test Architecture for TSV With Resistive Open Defects in 3-D Stacked Memories.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2014

2013

A Die Selection and Matching Method with Two Stages for Yield Enhancement of 3-D Memories.

[BibT_eX]

[DOI]

Proceedings of the 22nd Asian Test Symposium, 2013

Keewon Cho

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