Jieun Jang
Orcid: 0000-0003-0224-6154
According to our database1,
Jieun Jang
authored at least 10 papers
between 2018 and 2023.
Collaborative distances:
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Bibliography
2023
A 192-Gb 12-High 896-GB/s HBM3 DRAM With a TSV Auto-Calibration Scheme and Machine-Learning-Based Layout Optimization.
IEEE J. Solid State Circuits, 2023
A 1ynm 1.25V 8Gb 16Gb/s/Pin GDDR6-Based Accelerator-in-Memory Supporting 1TFLOPS MAC Operation and Various Activation Functions for Deep Learning Application.
IEEE J. Solid State Circuits, 2023
2022
A Clock Distribution Scheme Insensitive to Supply Voltage Drift With Self-Adjustment of Clock Buffer Delay.
IEEE Trans. Circuits Syst. II Express Briefs, 2022
A 24-Gb/s/Pin 8-Gb GDDR6 With a Half-Rate Daisy-Chain-Based Clocking Architecture and I/O Circuitry for Low-Noise Operation.
IEEE J. Solid State Circuits, 2022
A 192-Gb 12-High 896-GB/s HBM3 DRAM with a TSV Auto-Calibration Scheme and Machine-Learning-Based Layout Optimization.
Proceedings of the IEEE International Solid-State Circuits Conference, 2022
A 1ynm 1.25V 8Gb, 16Gb/s/pin GDDR6-based Accelerator-in-Memory supporting 1TFLOPS MAC Operation and Various Activation Functions for Deep-Learning Applications.
Proceedings of the IEEE International Solid-State Circuits Conference, 2022
2018
A Compact Resistor-Based CMOS Temperature Sensor With an Inaccuracy of 0.12 °C (3σ) and a Resolution FoM of 0.43 pJ⋅K<sup>2</sup> in 65-nm CMOS.
IEEE J. Solid State Circuits, 2018
A 16Gb 1.2V 3.2Gb/s/pin DDR4 SDRAM with improved power distribution and repair strategy.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018
A 0.53pJK<sup>2</sup> 7000μm<sup>2</sup> resistor-based temperature sensor with an inaccuracy of ±0.35°C (3σ) in 65nm CMOS.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018
Design Considerations of Monolithically Integrated Voltage Regulators for Multicore Processors.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018