Junhyun Chun
According to our database1,
Junhyun Chun
authored at least 17 papers
between 2018 and 2023.
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Bibliography
2023
A 1ynm 1.25V 8Gb 16Gb/s/Pin GDDR6-Based Accelerator-in-Memory Supporting 1TFLOPS MAC Operation and Various Activation Functions for Deep Learning Application.
IEEE J. Solid State Circuits, 2023
Proceedings of the 35th IEEE Hot Chips Symposium, 2023
2022
A 24-Gb/s/Pin 8-Gb GDDR6 With a Half-Rate Daisy-Chain-Based Clocking Architecture and I/O Circuitry for Low-Noise Operation.
IEEE J. Solid State Circuits, 2022
A 192-Gb 12-High 896-GB/s HBM3 DRAM with a TSV Auto-Calibration Scheme and Machine-Learning-Based Layout Optimization.
Proceedings of the IEEE International Solid-State Circuits Conference, 2022
A 1ynm 1.25V 8Gb, 16Gb/s/pin GDDR6-based Accelerator-in-Memory supporting 1TFLOPS MAC Operation and Various Activation Functions for Deep-Learning Applications.
Proceedings of the IEEE International Solid-State Circuits Conference, 2022
Proceedings of the 2022 IEEE Hot Chips 34 Symposium, 2022
2021
A 1.3-4-GHz Quadrature-Phase Digital DLL Using Sequential Delay Control and Reconfigurable Delay Line.
IEEE J. Solid State Circuits, 2021
A 24Gb/s/pin 8Gb GDDR6 with a Half-Rate Daisy-Chain-Based Clocking Architecture and IO Circuitry for Low-Noise Operation.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021
Process-Portable and Programmable Layout Generation of Digital Circuits in Advanced DRAM Technologies.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021
2020
A 1.1-V 10-nm Class 6.4-Gb/s/Pin 16-Gb DDR5 SDRAM With a Phase Rotator-ILO DLL, High-Speed SerDes, and DFE/FFE Equalization Scheme for Rx/Tx.
IEEE J. Solid State Circuits, 2020
22.3 A 128Gb 8-High 512GB/s HBM2E DRAM with a Pseudo Quarter Bank Structure, Power Dispersion and an Instruction-Based At-Speed PMBIST.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020
2019
Proceedings of the IEEE International Solid- State Circuits Conference, 2019
A 1.1V 1ynm 6.4Gb/s/pin 16Gb DDR5 SDRAM with a Phase-Rotator-Based DLL, High-Speed SerDes and RX/TX Equalization Scheme.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019
2018
A Compact Resistor-Based CMOS Temperature Sensor With an Inaccuracy of 0.12 °C (3σ) and a Resolution FoM of 0.43 pJ⋅K<sup>2</sup> in 65-nm CMOS.
IEEE J. Solid State Circuits, 2018
A 16Gb 1.2V 3.2Gb/s/pin DDR4 SDRAM with improved power distribution and repair strategy.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018
A 16Gb/s/pin 8Gb GDDR6 DRAM with bandwidth extension techniques for high-speed applications.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018
A 0.53pJK<sup>2</sup> 7000μm<sup>2</sup> resistor-based temperature sensor with an inaccuracy of ±0.35°C (3σ) in 65nm CMOS.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018