Masahide Takada

According to our database, Masahide Takada authored at least 7 papers between 1990 and 1996.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

1996

A 6-ns, 1.5-V, 4-Mb BiCMOS SRAM.

Hideo Toyoshima, Shigeru Kuhara, Koichi Takeda, Kazuyuki Nakamura, Hiloshi Okamura, Masahide Takada, Hisamitsu Suzuki, Hiroshi Yoshida, Tohru Yamazaki

IEEE J. Solid State Circuits, 1996

A sub-2.0 V BiCMOS logic circuit with a BiCMOS charge pump.

Hitoshi Okamura, Takao Atsumo, Koichi Takeda, Masahide Takada, Kiyotaka Imai, Yasushi Kinoshita, Tom Yamazaki

IEEE J. Solid State Circuits, 1996

A 60-ns 1-Mb nonvolatile ferroelectric memory with a nondriven cell plate line write/read scheme.

Hiraki Koike, Tetsuya Otsuki, Tohru Kimura, Masao Fukuma, Yoshihira Hayashi, Yukihiko Maejima, Kazushi Amanuma, Nobuhira Tanabe, Takeo Matsuki, Shinobu Saito, Tsuneo Takeuchi, Souta Kobayashi, Takemitsu Kunio, Takashi Hase, Yoichi Miyasaka, Nobuaki Shohata, Masahide Takada

IEEE J. Solid State Circuits, 1996

1995

A 1 ns, 1 W, 2.5 V, 32 Kb NTL-CMOS SRAM macro using a memory cell with PMOS access transistors.

Hitoshi Okamura, Hideo Toyoshima, Koichi Takeda, Takashi Oguri, Satoshi Nakamura, Masahide Takada, Kiyotaka Imai, Yasushi Kinoshita, Hiroshi Yoshida, Tom Yamazaki

IEEE J. Solid State Circuits, November, 1995

1994

A 220-MHz pipelined 16-Mb BiCMOS SRAM with PLL proportional self-timing generator.

Kazuyuki Nakamura, Shigeru Kuhara, Tohru Kimura, Masahide Takada, Hisamitsu Suzuki, Hiroshi Yoshida, Tohru Yamazaki

IEEE J. Solid State Circuits, November, 1994

1993

Memory LSI reliability.

Masao Fukuma, Hiroshi Furuta, Masahide Takada

Proc. IEEE, 1993

1990

A BIST scheme using microprogram ROM for large capacity memories.

Hiroki Koike, Toshio Takeshima, Masahide Takada

Proceedings of the Proceedings IEEE International Test Conference 1990, 1990