Kouichi Kanda

According to our database1, Kouichi Kanda authored at least 18 papers between 2005 and 2020.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2020
A Permutational Boltzmann Machine with Parallel Tempering for Solving Combinatorial Optimization Problems.
Proceedings of the Parallel Problem Solving from Nature - PPSN XVI, 2020

2015
A 0.33 nJ/bit IEEE802.15.6/Proprietary MICS/ISM Wireless Transceiver With Scalable Data Rate for Medical Implantable Applications.
IEEE J. Biomed. Health Informatics, 2015

A 3.5mW 315/400MHz IEEE802.15.6/proprietary mode digitally-tunable radio SoC with integrated digital baseband and MAC processor in 40nm CMOS.
Proceedings of the Symposium on VLSI Circuits, 2015

2014
Radio channel characterization for 400 MHz implanted devices.
Proceedings of the IEEE Wireless Communications and Networking Conference, 2014

9.7 A 0.33nJ/b IEEE802.15.6/proprietary-MICS/ISM-band transceiver with scalable data-rate from 11kb/s to 4.5Mb/s for medical applications.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

2012

2011
A 60-GHz Injection-Locked Frequency Divider Using Multi-Order <i>LC</i> Oscillator Topology for Wide Locking Range.
IEICE Trans. Electron., 2011

2010
A 3 Watt 39.8-44.6 Gb/s Dual-Mode SFI5.2 SerDes Chip Set in 65 nm CMOS.
IEEE J. Solid State Circuits, 2010

A 60-GHz 1.65mW 25.9% locking range multi-order LC oscillator based injection locked frequency divider in 65nm CMOS.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2010

2009
A Single-40 Gb/s Dual-20 Gb/s Serializer IC With SFI-5.2 Interface in 65 nm CMOS.
IEEE J. Solid State Circuits, 2009

A single-40Gb/s dual-20Gb/s serializer IC with SFI-5.2 interface in 65nm CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2009

2008
20-GHz Quadrature Injection-Locked LC Dividers With Enhanced Locking Range.
IEEE J. Solid State Circuits, 2008

2007
18-GHz Clock Distribution Using a Coupled VCO Array.
IEICE Trans. Electron., 2007

A 4-Channel 3.1/10.3Gb/s Transceiver Macro with a Pattern-Tolerant Adaptive Equalizer.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

2006
Managing subthreshold leakage in charge-based analog circuits with low-V/sub TH/ transistors by analog T- switch (AT-switch) and super cut-off CMOS (SCCMOS).
IEEE J. Solid State Circuits, 2006

Circuits for CMOS High-Speed I/O in Sub-100 nm Technologies.
IEICE Trans. Electron., 2006

2005
Row-by-Row Dynamic Source-Line Voltage Control (RRDSV) Scheme for Two Orders of Magnitude Leakage Current Reduction of Sub-1-V-<i>V<sub>DD</sub></i> SRAM's.
IEICE Trans. Electron., 2005

Subthreshold-leakage suppressed switched capacitor circuit based on super cut-off CMOS (SCCMOS).
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005


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