Jung Yun Choi

According to our database1, Jung Yun Choi authored at least 12 papers between 2001 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

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Bibliography

2023
Accurate Layout-Dependent Effect Model in 10 nm-Class DRAM Process Using Area-Efficient Array Test Circuits.
IEEE Access, 2023

2021
Application of Deep Reinforcement Learning to Dynamic Verification of DRAM Designs.
Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021

2016
Sequential analysis driven reset optimization to improve power, area and routability.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

Adaptive delay monitoring for wide voltage-range operation.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

2015
Coarse-grained Structural Placement for a Synthesized Parallel Multiplier.
Proceedings of the 2015 Symposium on International Symposium on Physical Design, ISPD 2015, Monterey, CA, USA, March 29, 2015

Clock domain crossing aware sequential clock gating.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

2013
Early-life-failure detection using SAT-based ATPG.
Proceedings of the 2013 IEEE International Test Conference, 2013

Detection of early-life failures in high-K metal-gate transistors and ultra low-K inter-metal dielectrics.
Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013

2010
Supply Switching With Ground Collapse for Low-Leakage Register Files in 65-nm CMOS.
IEEE Trans. Very Large Scale Integr. Syst., 2010

2007
Supply Switching With Ground Collapse: Simultaneous Control of Subthreshold and Gate Leakage Current in Nanometer-Scale CMOS Circuits.
IEEE Trans. Very Large Scale Integr. Syst., 2007

Simultaneous Control of Subthreshold and Gate Leakage Current in Nanometer-Scale CMOS Circuits.
Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007

2001
Backward Propagated Capacitance Model for Register Transfer Level Power Estimation.
VLSI Design, 2001


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