Kyungmin Baek

Orcid: 0009-0009-9539-4287

According to our database¹, Kyungmin Baek authored at least 4 papers between 2022 and 2025.

Collaborative distances:

Dijkstra number² of five.
Erdős number³ of four.

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Bibliography

2025

A Supply Noise-Insensitive Ring DCO With a Self-Biased Shunt Regulator Array in Wide-Range Digital PLL.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., August, 2025

2023

A 48-Gb/s Single-Ended PAM-4 Receiver with Adaptive Nonlinearity Compensation.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

A PAM4 Level Mismatch Adjustment Scheme for 48-Gb/s PAM4 Memory Tester Bridge.

[BibT_eX]

[DOI]

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2023

2022

A 5GHz All-Digital PLL with shunt regulating Ring DCO in BOST for DDR5 ATE.

[BibT_eX]

[DOI]

Kyungmin Baek

Kahyun Kim

Deog-Kyoon Jeong

Proceedings of the 19th International SoC Design Conference, 2022

Kyungmin Baek

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