Laith A. Shamieh

Orcid: 0009-0006-2195-7479

According to our database1, Laith A. Shamieh authored at least 6 papers between 2024 and 2026.

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Bibliography

2026
A 256-Element Slepian Beamforming Accelerator With Analog Compute-In-Memory Multiplication and Accumulation.
IEEE Solid State Circuits Lett., 2026

A 194.6-TOPS/W Pipelined All Current-Domain Mixed-Signal Compute in Memory in 28-nm CMOS.
IEEE Solid State Circuits Lett., 2026

A 92.5 TOPS/W Fully-Analog Multi-Layer Computing-in-Memory for State-Space Models in 28nm CMOS.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2026

2025
MIX-ACIM: A 28-nm Mixed-Precision Analog Compute-in-Memory With Digital Feature Restoration for Vector-Matrix Multiplication.
IEEE Solid State Circuits Lett., 2025

Low-Latency Digital Feedback for Stochastic Quantum Calibration Using Cryogenic CMOS.
Proceedings of the Design, Automation & Test in Europe Conference, 2025

2024
Cryogenic Operation of Computing-In-Memory based Spiking Neural Network.
Proceedings of the 29th ACM/IEEE International Symposium on Low Power Electronics and Design, 2024


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