Lee Whetsel

According to our database1, Lee Whetsel authored at least 24 papers between 1988 and 2010.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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In proceedings 
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PhD thesis 
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Links

On csauthors.net:

Bibliography

2010
Commanded Test Access Port operations.
Proceedings of the 2011 IEEE International Test Conference, 2010

2006
A High Speed Reduced Pin Count JTAG Interface.
Proceedings of the 2006 IEEE International Test Conference, 2006

2003
Adapting JTAG for AC Interconnect Testing.
Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003

Evolution of IEEE 1149.1 Addressable Shadow Protocol Devices.
Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003

Overview of the IEEE P1500 Standard.
Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003

2002
Inevitable Use of TAP Domains in SOCs.
Proceedings of the Proceedings IEEE International Test Conference 2002, 2002

2001
An analysis of power reduction techniques in scan testing.
Proceedings of the Proceedings IEEE International Test Conference 2001, Baltimore, MD, USA, 30 October, 2001

2000
Adapting scan architectures for low power operation.
Proceedings of the Proceedings IEEE International Test Conference 2000, 2000

1999
Towards a standard for embedded core test: an example.
Proceedings of the Proceedings IEEE International Test Conference 1999, 1999

Addressable test ports an approach to testing embedded cores.
Proceedings of the Proceedings IEEE International Test Conference 1999, 1999

1998
Core test connectivity, communication, and control.
Proceedings of the Proceedings IEEE International Test Conference 1998, 1998

1997
A silicon El Niño?
IEEE Des. Test Comput., 1997

Test Access of TAP'ed & Non-TAP'ed Cores.
Proceedings of the Proceedings IEEE International Test Conference 1997, 1997

An IEEE 1149.1-Based Test Access Architecture for ICs with Embedded Cores.
Proceedings of the Proceedings IEEE International Test Conference 1997, 1997

1996
Proposal to Simplify Development of a Mixed-Signal Test Standard.
Proceedings of the Proceedings IEEE International Test Conference 1996, 1996

1995
Improved Boundary Scan Design.
Proceedings of the Proceedings IEEE International Test Conference 1995, 1995

1994
Navigating Test Access in Systems.
Proceedings of the Proceedings IEEE International Test Conference 1994, 1994

An Approach to Accelerate Scan Testing in IEEE 1149.1 Architectures.
Proceedings of the Proceedings IEEE International Test Conference 1994, 1994

1993
An IEEE 1149.1 based voltmeter/oscilloscope in a chip.
Proceedings of the 11th IEEE VLSI Test Symposium (VTS'93), 1993

Hierarchically Accessing 1149.1 Applications in a System Environment.
Proceedings of the Proceedings IEEE International Test Conference 1993, Designing, Testing, and Diagnostics, 1993

1992
A Proposed Method of Accessing 1149.1 in a Backplane Environment.
Proceedings of the Proceedings IEEE International Test Conference 1992, 1992

1991
An IEEE 1149.1 Based Logic/Signature Analyzer in a Chip.
Proceedings of the Proceedings IEEE International Test Conference 1991, 1991

1990
Event qualification: a gateway to at-speed system testing.
Proceedings of the Proceedings IEEE International Test Conference 1990, 1990

1988
A proposed standard test bus and boundary scan architecture.
Proceedings of the Computer Design: VLSI in Computers and Processors, 1988


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