Erik Jan Marinissen

According to our database1, Erik Jan Marinissen authored at least 130 papers between 1998 and 2020.

Collaborative distances:

Awards

IEEE Fellow

IEEE Fellow 2011, "For contributions to modular testing of core-based system chips".

Timeline

Legend:

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Article 
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On csauthors.net:

Bibliography

2020
Survey on STT-MRAM Testing: Failure Mechanisms, Fault Models, and Tests.
CoRR, 2020

2019
Defect-Location Identification for Cell-Aware Test.
Proceedings of the IEEE Latin American Test Symposium, 2019

Optimization of Cell-Aware ATPG Results by Manipulating Library Cells' Defect Detection Matrices.
Proceedings of the IEEE International Test Conference in Asia, 2019

Pinhole Defect Characterization and Fault Modeling for STT-MRAM Testing.
Proceedings of the 24th IEEE European Test Symposium, 2019

2018
Electrical Modeling of STT-MRAM Defects.
Proceedings of the IEEE International Test Conference, 2018

Solutions to Multiple Probing Challenges for Test Access to Multi-Die Stacked Integrated Circuits.
Proceedings of the IEEE International Test Conference, 2018

On-Chip Toggle Generators to Provide Realistic Conditions during Test of Digital 2D-SoCs and 3D-SICs.
Proceedings of the IEEE International Test Conference, 2018

Automatic generation of in-circuit tests for board assembly defects.
Proceedings of the 23rd IEEE European Test Symposium, 2018

IEEE Std P1838's flexible parallel port and its specification with Google's protocol buffers.
Proceedings of the 23rd IEEE European Test Symposium, 2018

2017
Guest Editors' Introduction: Design & Test of a High-Volume 3-D Stacked Graphics Processor With High-Bandwidth Memory.
IEEE Design & Test, 2017

Embedded toggle generator to control the switching activity during test of digital 2D-SoCs and 3D-SICs.
Proceedings of the 27th International Symposium on Power and Timing Modeling, 2017

A fully automatic test system for characterizing large-array fine-pitch micro-bump probe cards.
Proceedings of the International Test Conference in Asia, 2017

2016
Guest Editors' Introduction: Robust 3-D Stacked ICs.
IEEE Design & Test, 2016


IEEE Std P1838: DfT standard-under-development for 2.5D-, 3D-, and 5.5D-SICs.
Proceedings of the 21th IEEE European Test Symposium, 2016

Test-station for flexible semi-automatic wafer-level silicon photonics testing.
Proceedings of the 21th IEEE European Test Symposium, 2016

2015
Yield Improvement for 3D Wafer-to-Wafer Stacked ICs Using Wafer Matching.
ACM Trans. Design Autom. Electr. Syst., 2015

Post-Bond Interconnect Test and Diagnosis for 3-D Memory Stacked on Logic.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2015

Robust Optimization of Test-Access Architectures Under Realistic Scenarios.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2015

Abort-on-Fail Test Scheduling for Modular SOCs without and with Preemption.
IEEE Trans. Computers, 2015

A DfT Architecture and Tool Flow for 3-D SICs With Test Data Compression, Embedded Cores, and Multiple Towers.
IEEE Design & Test, 2015


Automated testing of bare die-to-die stacks.
Proceedings of the 2015 IEEE International Test Conference, 2015

At-Speed Testing of Inter-Die Connections of 3D-SICs in the Presence of Shore Logic.
Proceedings of the 24th IEEE Asian Test Symposium, 2015

Processing active devices on Si interposer and impact on cost.
Proceedings of the 2015 International 3D Systems Integration Conference, 2015

2014
Low-Cost Post-Bond Testing of 3-D ICs Containing a Passive Silicon Interposer Base.
IEEE Trans. VLSI Syst., 2014

Quality versus cost analysis for 3D Stacked ICs.
Proceedings of the 32nd IEEE VLSI Test Symposium, 2014

Direct probing on large-array fine-pitch micro-bumps of a wide-I/O logic-memory interface.
Proceedings of the 2014 International Test Conference, 2014

Vesuvius-3D: A 3D-DfT demonstrator.
Proceedings of the 2014 International Test Conference, 2014

Interconnect test for 3D stacked memory-on-logic.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

2013
Uncertainty-aware robust optimization of test-access architectures for 3D stacked ICs.
Proceedings of the 2013 IEEE International Test Conference, 2013

Murphy goes 3D.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2013

Automated DfT insertion and test generation for 3D-SICs with embedded cores and multiple towers.
Proceedings of the 18th IEEE European Test Symposium, 2013

Impact of mid-bond testing in 3D stacked ICs.
Proceedings of the 2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2013

Creating options for 3D-SIC testing.
Proceedings of the 16th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2013

Design issues in heterogeneous 3D/2.5D integration.
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013

Si interposer build-up options and impact on 3D system cost.
Proceedings of the 2013 IEEE International 3D Systems Integration Conference (3DIC), 2013

Using 3D-COSTAR for 2.5D test cost optimization.
Proceedings of the 2013 IEEE International 3D Systems Integration Conference (3DIC), 2013

2012
Test Impact on the Overall Die-to-Wafer 3D Stacked IC Cost.
J. Electronic Testing, 2012

Optimization Methods for Post-Bond Testing of 3D Stacked ICs.
J. Electronic Testing, 2012

Guest Editorial: Special Issue on Testing of 3D Stacked Integrated Circuits.
J. Electronic Testing, 2012

A DfT Architecture for 3D-SICs Based on a Standardizable Die Wrapper.
J. Electronic Testing, 2012

Pioneering in Asia With the US Venture Capital Model.
IEEE Design & Test of Computers, 2012

DfT architecture and ATPG for Interconnect tests of JEDEC Wide-I/O memory-on-logic die stacks.
Proceedings of the 2012 IEEE International Test Conference, 2012

EDA solutions to new-defect detection in advanced process technologies.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

Challenges and emerging solutions in testing TSV-based 2 1 over 2D- and 3D-stacked ICs.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

2011
Testing 3D Stacked ICs Containing Through-Silicon Vias.
Proceedings of the 3D Integration for NoC-based SoC Architectures, 2011

Test-Architecture Optimization and Test Scheduling for TSV-Based 3-D Stacked ICs.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2011

Evaluation of TSV and micro-bump probing for wide I/O testing.
Proceedings of the 2011 IEEE International Test Conference, 2011

Post-bond testing of 2.5D-SICs and 3D-SICs containing a passive silicon interposer base.
Proceedings of the 2011 IEEE International Test Conference, 2011

On modeling and optimizing cost in 3D Stacked-ICs.
Proceedings of the 6th IEEE International Design and Test Workshop, 2011

DfT Architecture for 3D-SICs with Multiple Towers.
Proceedings of the 16th European Test Symposium, 2011

Automation of 3D-DfT Insertion.
Proceedings of the 20th IEEE Asian Test Symposium, 2011

Multi-visit TAMs to Reduce the Post-Bond Test Length of 2.5D-SICs with a Passive Silicon Interposer Base.
Proceedings of the 20th IEEE Asian Test Symposium, 2011

2010
Bandwidth Analysis of Functional Interconnects Used as Test Access Mechanism.
J. Electronic Testing, 2010

A structured and scalable test access architecture for TSV-based 3D stacked ICs.
Proceedings of the 28th IEEE VLSI Test Symposium, 2010

On maximizing the compound yield for 3D Wafer-to-Wafer stacked ICs.
Proceedings of the 2011 IEEE International Test Conference, 2010

Optimization methods for post-bond die-internal/external testing in 3D stacked ICs.
Proceedings of the 2011 IEEE International Test Conference, 2010

3D integration: Circuit design, test, and reliability challenges.
Proceedings of the 16th IEEE International On-Line Testing Symposium (IOLTS 2010), 2010

On the cost-effectiveness of matching repositories of pre-tested wafers for wafer-to-wafer 3D chip stacking.
Proceedings of the 15th European Test Symposium, 2010

Test-architecture optimization for TSV-based 3D stacked ICs.
Proceedings of the 15th European Test Symposium, 2010

Adapting to adaptive testing.
Proceedings of the Design, Automation and Test in Europe, 2010

Testing TSV-based three-dimensional stacked ICs.
Proceedings of the Design, Automation and Test in Europe, 2010

Test Cost Analysis for 3D Die-to-Wafer Stacking.
Proceedings of the 19th IEEE Asian Test Symposium, 2010

Challenges in testing TSV-based 3D stacked ICs: Test flows, test contents, and test access.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2010

Cost effectiveness of 3D integration options.
Proceedings of the IEEE International Conference on 3D System Integration, 2010

3D DfT architecture for pre-bond and post-bond testing.
Proceedings of the IEEE International Conference on 3D System Integration, 2010

2009
Testing of SoCs with Hierarchical Cores: Common Fallacies, Test Access Optimization, and Test Scheduling.
IEEE Trans. Computers, 2009

Test Data Volume Comparison: Monolithic vs. Modular SoC Testing.
IEEE Design & Test of Computers, 2009

Guest Editors' Introduction: The Status of IEEE Std 1500 - Part 2.
IEEE Design & Test of Computers, 2009

IEEE Std 1500 Enables Modular SoC Testing.
IEEE Design & Test of Computers, 2009

Guest Editors' Introduction: The Status of IEEE Std 1500.
IEEE Design & Test of Computers, 2009

Testing 3D chips containing through-silicon vias.
Proceedings of the 2009 IEEE International Test Conference, 2009

Contactless testing: Possibility or pipe-dream?
Proceedings of the Design, Automation and Test in Europe, 2009

On Scan Chain Diagnosis for Intermittent Faults.
Proceedings of the Eighteentgh Asian Test Symposium, 2009

Impact of 3D design choices on manufacturing cost.
Proceedings of the IEEE International Conference on 3D System Integration, 2009

2008
Bugs, moths, grasshoppers, and whales.
IEEE Design & Test of Computers, 2008

Guest Editors' Introduction: Addressing the Challenges of Debug and Diagnosis.
IEEE Design & Test of Computers, 2008

Bandwidth Analysis for Reusing Functional Interconnect as Test Access Mechanism.
Proceedings of the 13th European Test Symposium, 2008

Analysis of The Test Data Volume Reduction Benefit of Modular SOC Testing.
Proceedings of the Design, Automation and Test in Europe, 2008

2007
Editorial Silicon Debug and Diagnosis.
IET Computers & Digital Techniques, 2007

Editorial.
IET Computers & Digital Techniques, 2007

Wrapper design for the reuse of a bus, network-on-chip, or other functional interconnect as test access mechanism.
IET Computers & Digital Techniques, 2007

DATE 07 workshop on diagnostic services in NoCs.
IEEE Design & Test of Computers, 2007

Embedded multi-detect ATPG and Its Effect on the Detection of Unmodeled Defects.
Proceedings of the 2007 IEEE International Test Conference, 2007

Design and DfT of a high-speed area-efficient embedded asynchronous FIFO.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

Test quality analysis and improvement for an embedded asynchronous FIFO.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

2006
Conference Reports.
IEEE Design & Test of Computers, 2006

Wrapper Design for the Reuse of Networks-on-Chip as Test Access Mechanism.
Proceedings of the 11th European Test Symposium, 2006

Hierarchy-aware and area-efficient test infrastructure design for core-based system chips.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006

2005
Optimal Interconnect ATPG Under a Ground-Bounce Constraint.
J. Electronic Testing, 2005

Test scheduling for modular SOCs in an abort-on-fail environment.
Proceedings of the 10th European Test Symposium, ETS 2005, Tallinn, 2005

Challenges in Embedded Memory Design and Test.
Proceedings of the 2005 Design, 2005

On-Chip Test Infrastructure Design for Optimal Multi-Site Testing of System Chips.
Proceedings of the 2005 Design, 2005

IEEE Std 1500 Compliant Infrastructure forModular SOC Testing.
Proceedings of the 14th Asian Test Symposium (ATS 2005), 2005

2004
Trends in Testing Integrated Circuits.
Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004

IEEE P1500-Compliant Test Wrapper Design for Hierarchical Cores.
Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004

Security vs. Test Quality: Can We Really Only Have One at a Time?
Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004

User-constrained test architecture design for modular SOC testing.
Proceedings of the 9th European Test Symposium, 2004

Test Infrastructure Design for the Nexperia? Home Platform PNX8550 System Chip.
Proceedings of the 2004 Design, 2004

Infrastructure for modular SOC testing.
Proceedings of the IEEE 2004 Custom Integrated Circuits Conference, 2004

2003
SOC test architecture design for efficient utilization of test bandwidth.
ACM Trans. Design Autom. Electr. Syst., 2003

Efficient test access mechanism optimization for system-on-chip.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2003

Test Access Mechanism Optimization, Test Scheduling, and Tester Data Volume Reduction for System-on-Chip.
IEEE Trans. Computers, 2003

A Test Time Reduction Algorithm for Test Architecture Design for Core-Based System Chips.
J. Electronic Testing, 2003

Minimizing Pattern Count for Interconnect Test under a Ground Bounce Constraint.
IEEE Design & Test of Computers, 2003

Creating Value Through Test.
Proceedings of the 2003 Design, 2003

Layout-Driven SOC Test Architecture Design for Test Time and Wire Length Minimization.
Proceedings of the 2003 Design, 2003

2002
On IEEE P1500's Standard for Embedded Core Test.
J. Electronic Testing, 2002

The Role of Test Protocols in Automated Test Generation for Embedded-Core-Based System ICs.
J. Electronic Testing, 2002

Test Wrapper and Test Access Mechanism Co-Optimization for System-on-Chip.
J. Electronic Testing, 2002

How Useful are the ITC 02 SoC Test Benchmarks?
IEEE Design & Test of Computers, 2002

On Using Rectangle Packing for SOC Wrapper/TAM Co-Optimization.
Proceedings of the 20th IEEE VLSI Test Symposium (VTS 2002), Without Testing It's a Gamble, 28 April, 2002

Cluster-Based Test Architecture Design for System-on-Chip.
Proceedings of the 20th IEEE VLSI Test Symposium (VTS 2002), Without Testing It's a Gamble, 28 April, 2002

A Set of Benchmarks fo Modular Testing of SOCs.
Proceedings of the Proceedings IEEE International Test Conference 2002, 2002

Test Resource Optimization for Multi-Site Testing of SOCs Under ATE Memory Depth Constraints.
Proceedings of the Proceedings IEEE International Test Conference 2002, 2002

Effective and Efficient Test Architecture Design for SOCs.
Proceedings of the Proceedings IEEE International Test Conference 2002, 2002

Efficient Wrapper/TAM Co-Optimization for Large SOCs.
Proceedings of the 2002 Design, 2002

Wrapper/TAM co-optimization, constraint-driven test scheduling, and tester data volume reduction for SOCs.
Proceedings of the 39th Design Automation Conference, 2002

Recent Advances in Test Planning for Modular Testing of Core-Based SOCs.
Proceedings of the 11th Asian Test Symposium (ATS 2002), 18-20 November 2002, Guam, USA, 2002

2001
Application of Deterministic Logic BIST on Industrial Circuits.
J. Electronic Testing, 2001

An Industrial Approach to Core-Based System Chip Testing.
Proceedings of the SOC Design Methodologies, 2001

2000
Wrapper design for embedded core test.
Proceedings of the Proceedings IEEE International Test Conference 2000, 2000

On using IEEE P1500 SECT for test plug-n-play.
Proceedings of the Proceedings IEEE International Test Conference 2000, 2000

System chip test: how will it impact your design?
Proceedings of the 37th Conference on Design Automation, 2000

1999
Testing Embedded-Core-Based System Chips.
IEEE Computer, 1999

Challenges in testing core-based system ICs.
IEEE Communications Magazine, 1999

Towards a standard for embedded core test: an example.
Proceedings of the Proceedings IEEE International Test Conference 1999, 1999

1998
A structured and scalable mechanism for test access to embedded reusable cores.
Proceedings of the Proceedings IEEE International Test Conference 1998, 1998

Scan chain design for test time reduction in core-based ICs.
Proceedings of the Proceedings IEEE International Test Conference 1998, 1998


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