Erik Jan Marinissen

Proceedings of the IEEE International Test Conference in Asia, 2023

Generating Test Patterns for Chiplet Interconnects: Achieving Optimal Effectiveness and Efficiency.

[BibT_eX]

[DOI]

Po-Yao Chuang

Francesco Lorenzelli

Proceedings of the IEEE International Test Conference in Asia, 2023

Study of Transistor Metrics for Room-Temperature Screening of Single Electron Transistors for Silicon Spin Qubit Applications.

[BibT_eX]

[DOI]

Proceedings of the IEEE European Test Symposium, 2023

Device-Aware Test for Back-Hopping Defects in STT-MRAMs.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

Device Aware Diagnosis for Unique Defects in STT-MRAMs.

[BibT_eX]

[DOI]

Proceedings of the 32nd IEEE Asian Test Symposium, 2023

Effective and Efficient Test and Diagnosis Pattern Generation for Many Inter-Die Interconnects in Chiplet-Based Packages.

[BibT_eX]

[DOI]

Proceedings of the IEEE International 3D Systems Integration Conference, 2023

2022

A Bypassable Scan Flip-Flop for Low Power Testing With Data Retention Capability.

[BibT_eX]

[DOI]

Xugang Cao

Hailong Jiao

IEEE Trans. Circuits Syst. II Express Briefs, 2022

MFA-MTJ Model: Magnetic-Field-Aware Compact Model of pMTJ for Robust STT-MRAM Design.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

Characterization, Modeling, and Test of Intermediate State Defects in STT-MRAMs.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2022

Testing Embedded Toggle Generation Through On-Chip IR-Drop Measurements.

[BibT_eX]

[DOI]

IEEE Des. Test, 2022

Guest Editors' Introduction: Special Issue on Design and Test of Multidie Packages.

[BibT_eX]

[DOI]

Adam Cron

Hailong Jiao

IEEE Des. Test, 2022

2021

Defect and Fault Modeling Framework for STT-MRAM Testing.

[BibT_eX]

[DOI]

Lizhou Wu

Siddharth Rao

Guilherme Cardoso Medeiros

IEEE Trans. Emerg. Top. Comput., 2021

Reducing Library Characterization Time for Cell-aware Test while Maintaining Test Quality.

[BibT_eX]

[DOI]

J. Electron. Test., 2021

Automated Probe-Mark Analysis for Advanced Probe Technology Characterization.

[BibT_eX]

[DOI]

IEEE Des. Test, 2021

IEEE Standard 1838 Is on the Move.

[BibT_eX]

[DOI]

Adam Cron

Computer, 2021

Testing STT-MRAM: Manufacturing Defects, Fault Models, and Test Solutions.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Test Conference, 2021

Testing Embedded Toggle Pattern Generation Through On-Chip IR Drop Monitoring.

[BibT_eX]

[DOI]

Proceedings of the 26th IEEE European Test Symposium, 2021

Speeding up Cell-Aware Library Characterization by Preceding Simulation with Structural Analysis.

[BibT_eX]

[DOI]

Proceedings of the 26th IEEE European Test Symposium, 2021

Characterization and Fault Modeling of Intermediate State Defects in STT-MRAM.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

2020

Survey on STT-MRAM Testing: Failure Mechanisms, Fault Models, and Tests.

[BibT_eX]

[DOI]

CoRR, 2020

Characterization, Modeling and Test of Synthetic Anti-Ferromagnet Flip Defect in STT-MRAMs.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Test Conference, 2020

Accurate Measurements of Small Resistances in Vertical Interconnects with Small Aspect Ratios.

[BibT_eX]

[DOI]

Michele Stucchi

Ferenc Fodor

Guilherme Cardoso Medeiros

Proceedings of the IEEE European Test Symposium, 2020

Tightening the Mesh Size of the Cell-Aware ATPG Net for Catching All Detectable Weakest Faults.

[BibT_eX]

[DOI]

Proceedings of the IEEE European Test Symposium, 2020

Impact of Magnetic Coupling and Density on STT-MRAM Performance.

[BibT_eX]

[DOI]

Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

2019

Defect-Location Identification for Cell-Aware Test.

[BibT_eX]

[DOI]

Proceedings of the IEEE Latin American Test Symposium, 2019

Application of Cell-Aware Test on an Advanced 3nm CMOS Technology Library.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Test Conference, 2019

Device-Aware Test: A New Test Approach Towards DPPB Level.

[BibT_eX]

[DOI]

Moritz Fieback

Lizhou Wu

Proceedings of the IEEE International Test Conference, 2019

Optimization of Cell-Aware ATPG Results by Manipulating Library Cells' Defect Detection Matrices.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Test Conference in Asia, 2019

Pinhole Defect Characterization and Fault Modeling for STT-MRAM Testing.

[BibT_eX]

[DOI]

Lizhou Wu

Siddharth Rao

Guilherme Cardoso Medeiros

Proceedings of the 24th IEEE European Test Symposium, 2019

Process Complexity and Cost Considerations of Multi-Layer Die Stacks.

[BibT_eX]

[DOI]

Stefaan Van Huylenbroeck

Proceedings of the 2019 International 3D Systems Integration Conference (3DIC), 2019

2018

Electrical Modeling of STT-MRAM Defects.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Test Conference, 2018

Solutions to Multiple Probing Challenges for Test Access to Multi-Die Stacked Integrated Circuits.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Test Conference, 2018

On-Chip Toggle Generators to Provide Realistic Conditions during Test of Digital 2D-SoCs and 3D-SICs.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Test Conference, 2018

Automatic generation of in-circuit tests for board assembly defects.

[BibT_eX]

[DOI]

Harm van Schaaijk

Martien Spierings

Proceedings of the 23rd IEEE European Test Symposium, 2018

IEEE Std P1838's flexible parallel port and its specification with Google's protocol buffers.

[BibT_eX]

[DOI]

Proceedings of the 23rd IEEE European Test Symposium, 2018

2017

Guest Editors' Introduction: Design & Test of a High-Volume 3-D Stacked Graphics Processor With High-Bandwidth Memory.

[BibT_eX]

[DOI]

IEEE Des. Test, 2017

Embedded toggle generator to control the switching activity during test of digital 2D-SoCs and 3D-SICs.

[BibT_eX]

[DOI]

Proceedings of the 27th International Symposium on Power and Timing Modeling, 2017

A fully automatic test system for characterizing large-array fine-pitch micro-bump probe cards.

[BibT_eX]

[DOI]

Proceedings of the International Test Conference in Asia, 2017

2016

Guest Editors' Introduction: Robust 3-D Stacked ICs.

[BibT_eX]

[DOI]

IEEE Des. Test, 2016

IoT: Source of test challenges.

[BibT_eX]

[DOI]

Proceedings of the 21th IEEE European Test Symposium, 2016

IEEE Std P1838: DfT standard-under-development for 2.5D-, 3D-, and 5.5D-SICs.

[BibT_eX]

[DOI]

Teresa L. McLaurin

Hailong Jiao

Proceedings of the 21th IEEE European Test Symposium, 2016

Test-station for flexible semi-automatic wafer-level silicon photonics testing.

[BibT_eX]

[DOI]

Proceedings of the 21th IEEE European Test Symposium, 2016

2015

Yield Improvement for 3D Wafer-to-Wafer Stacked ICs Using Wafer Matching.

[BibT_eX]

[DOI]

Said Hamdioui

ACM Trans. Design Autom. Electr. Syst., 2015

Post-Bond Interconnect Test and Diagnosis for 3-D Memory Stacked on Logic.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

Robust Optimization of Test-Access Architectures Under Realistic Scenarios.

[BibT_eX]

[DOI]

Sergej Deutsch

Muriel de Potter de ten Broeck

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

Abort-on-Fail Test Scheduling for Modular SOCs without and with Preemption.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2015

A DfT Architecture and Tool Flow for 3-D SICs With Test Data Compression, Embedded Cores, and Multiple Towers.

[BibT_eX]

[DOI]

IEEE Des. Test, 2015

Active-lite interposer for 2.5 & 3D integration.

[BibT_eX]

[DOI]

C. Roda Neve

Y. Li

Stefaan Van Huylenbroeck

Proceedings of the Symposium on VLSI Circuits, 2015

Automated testing of bare die-to-die stacks.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE International Test Conference, 2015

At-Speed Testing of Inter-Die Connections of 3D-SICs in the Presence of Shore Logic.

[BibT_eX]

[DOI]

Proceedings of the 24th IEEE Asian Test Symposium, 2015

Processing active devices on Si interposer and impact on cost.

[BibT_eX]

[DOI]

Proceedings of the 2015 International 3D Systems Integration Conference, 2015

2014

Low-Cost Post-Bond Testing of 3-D ICs Containing a Passive Silicon Interposer Base.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2014

Quality versus cost analysis for 3D Stacked ICs.

[BibT_eX]

[DOI]

Said Hamdioui

Proceedings of the 32nd IEEE VLSI Test Symposium, 2014

Direct probing on large-array fine-pitch micro-bumps of a wide-I/O logic-memory interface.

[BibT_eX]

[DOI]

Proceedings of the 2014 International Test Conference, 2014

Vesuvius-3D: A 3D-DfT demonstrator.

[BibT_eX]

[DOI]

Proceedings of the 2014 International Test Conference, 2014

Interconnect test for 3D stacked memory-on-logic.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

2013

Uncertainty-aware robust optimization of test-access architectures for 3D stacked ICs.

[BibT_eX]

[DOI]

Sergej Deutsch

Proceedings of the 2013 IEEE International Test Conference, 2013

Murphy goes 3D.

[BibT_eX]

[DOI]

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2013

Automated DfT insertion and test generation for 3D-SICs with embedded cores and multiple towers.

[BibT_eX]

[DOI]

Proceedings of the 18th IEEE European Test Symposium, 2013

Impact of mid-bond testing in 3D stacked ICs.

[BibT_eX]

[DOI]

Proceedings of the 2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2013

Creating options for 3D-SIC testing.

[BibT_eX]

[DOI]

Proceedings of the 16th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2013

Design issues in heterogeneous 3D/2.5D integration.

[BibT_eX]

[DOI]

Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013

Si interposer build-up options and impact on 3D system cost.

[BibT_eX]

[DOI]

Proceedings of the 2013 IEEE International 3D Systems Integration Conference (3DIC), 2013

Using 3D-COSTAR for 2.5D test cost optimization.

[BibT_eX]

[DOI]

Proceedings of the 2013 IEEE International 3D Systems Integration Conference (3DIC), 2013

2012

Test Impact on the Overall Die-to-Wafer 3D Stacked IC Cost.

[BibT_eX]

[DOI]

J. Electron. Test., 2012

Optimization Methods for Post-Bond Testing of 3D Stacked ICs.

[BibT_eX]

[DOI]

J. Electron. Test., 2012

Guest Editorial: Special Issue on Testing of 3D Stacked Integrated Circuits.

[BibT_eX]

[DOI]

J. Electron. Test., 2012

A DfT Architecture for 3D-SICs Based on a Standardizable Die Wrapper.

[BibT_eX]

[DOI]

J. Electron. Test., 2012

Pioneering in Asia With the US Venture Capital Model.

[BibT_eX]

[DOI]

IEEE Des. Test Comput., 2012

DfT architecture and ATPG for Interconnect tests of JEDEC Wide-I/O memory-on-logic die stacks.

[BibT_eX]

[DOI]

Proceedings of the 2012 IEEE International Test Conference, 2012

EDA solutions to new-defect detection in advanced process technologies.

[BibT_eX]

[DOI]

Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

Challenges and emerging solutions in testing TSV-based 2 1 over 2D- and 3D-stacked ICs.

[BibT_eX]

[DOI]

Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

2011

Testing 3D Stacked ICs Containing Through-Silicon Vias.

[BibT_eX]

[DOI]

Proceedings of the 3D Integration for NoC-based SoC Architectures, 2011

Test-Architecture Optimization and Test Scheduling for TSV-Based 3-D Stacked ICs.

[BibT_eX]

[DOI]

Jouke Verbree

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011

Evaluation of TSV and micro-bump probing for wide I/O testing.

[BibT_eX]

[DOI]

Proceedings of the 2011 IEEE International Test Conference, 2011

Post-bond testing of 2.5D-SICs and 3D-SICs containing a passive silicon interposer base.

[BibT_eX]

[DOI]

Proceedings of the 2011 IEEE International Test Conference, 2011

On modeling and optimizing cost in 3D Stacked-ICs.

[BibT_eX]

[DOI]

Said Hamdioui

Proceedings of the 6th IEEE International Design and Test Workshop, 2011

DfT Architecture for 3D-SICs with Multiple Towers.

[BibT_eX]

[DOI]

Proceedings of the 16th European Test Symposium, 2011

Automation of 3D-DfT Insertion.

[BibT_eX]

[DOI]

Proceedings of the 20th IEEE Asian Test Symposium, 2011

Multi-visit TAMs to Reduce the Post-Bond Test Length of 2.5D-SICs with a Passive Silicon Interposer Base.

[BibT_eX]

[DOI]

Proceedings of the 20th IEEE Asian Test Symposium, 2011

2010

Bandwidth Analysis of Functional Interconnects Used as Test Access Mechanism.

[BibT_eX]

[DOI]

J. Electron. Test., 2010

A structured and scalable test access architecture for TSV-based 3D stacked ICs.

[BibT_eX]

[DOI]

Jouke Verbree

Mario Konijnenburg

Proceedings of the 28th IEEE VLSI Test Symposium, 2010

On maximizing the compound yield for 3D Wafer-to-Wafer stacked ICs.

[BibT_eX]

[DOI]

Proceedings of the 2011 IEEE International Test Conference, 2010

Optimization methods for post-bond die-internal/external testing in 3D stacked ICs.

[BibT_eX]

[DOI]

Proceedings of the 2011 IEEE International Test Conference, 2010

3D integration: Circuit design, test, and reliability challenges.

[BibT_eX]

[DOI]

Proceedings of the 16th IEEE International On-Line Testing Symposium (IOLTS 2010), 2010

On the cost-effectiveness of matching repositories of pre-tested wafers for wafer-to-wafer 3D chip stacking.

[BibT_eX]

[DOI]

Proceedings of the 15th European Test Symposium, 2010

Test-architecture optimization for TSV-based 3D stacked ICs.

[BibT_eX]

[DOI]

Jouke Verbree

Proceedings of the 15th European Test Symposium, 2010

Adapting to adaptive testing.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2010

Testing TSV-based three-dimensional stacked ICs.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2010

Test Cost Analysis for 3D Die-to-Wafer Stacking.

[BibT_eX]

[DOI]

Proceedings of the 19th IEEE Asian Test Symposium, 2010

Challenges in testing TSV-based 3D stacked ICs: Test flows, test contents, and test access.

[BibT_eX]

[DOI]

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2010

Cost effectiveness of 3D integration options.

[BibT_eX]

[DOI]

Dimitrios Velenis

Eric Beyne

Proceedings of the IEEE International Conference on 3D System Integration, 2010

3D DfT architecture for pre-bond and post-bond testing.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on 3D System Integration, 2010

2009

Testing of SoCs with Hierarchical Cores: Common Fallacies, Test Access Optimization, and Test Scheduling.

[BibT_eX]

[DOI]

Anuja Sehgal

IEEE Trans. Computers, 2009

Test Data Volume Comparison: Monolithic vs. Modular SoC Testing.

[BibT_eX]

[DOI]

IEEE Des. Test Comput., 2009

Guest Editors' Introduction: The Status of IEEE Std 1500 - Part 2.

[BibT_eX]

[DOI]

IEEE Des. Test Comput., 2009

IEEE Std 1500 Enables Modular SoC Testing.

[BibT_eX]

[DOI]

IEEE Des. Test Comput., 2009

Guest Editors' Introduction: The Status of IEEE Std 1500.

[BibT_eX]

[DOI]

IEEE Des. Test Comput., 2009

Testing 3D chips containing through-silicon vias.

[BibT_eX]

[DOI]

Proceedings of the 2009 IEEE International Test Conference, 2009

Contactless testing: Possibility or pipe-dream?

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2009

On Scan Chain Diagnosis for Intermittent Faults.

[BibT_eX]

[DOI]

Proceedings of the Eighteentgh Asian Test Symposium, 2009

Impact of 3D design choices on manufacturing cost.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on 3D System Integration, 2009

2008

Bugs, moths, grasshoppers, and whales.

[BibT_eX]

[DOI]

IEEE Des. Test Comput., 2008

Guest Editors' Introduction: Addressing the Challenges of Debug and Diagnosis.

[BibT_eX]

[DOI]

Rob Aitken

IEEE Des. Test Comput., 2008

Bandwidth Analysis for Reusing Functional Interconnect as Test Access Mechanism.

[BibT_eX]

[DOI]

Proceedings of the 13th European Test Symposium, 2008

Analysis of The Test Data Volume Reduction Benefit of Modular SOC Testing.

[BibT_eX]

[DOI]

Ozgur Sinanoglu

Proceedings of the Design, Automation and Test in Europe, 2008

2007

Editorial Silicon Debug and Diagnosis.

[BibT_eX]

[DOI]

Nicola Nicolici

IET Comput. Digit. Tech., 2007

Editorial.

[BibT_eX]

[DOI]

Christian Landrault

IET Comput. Digit. Tech., 2007

Wrapper design for the reuse of a bus, network-on-chip, or other functional interconnect as test access mechanism.

[BibT_eX]

[DOI]

IET Comput. Digit. Tech., 2007

DATE 07 workshop on diagnostic services in NoCs.

[BibT_eX]

[DOI]

Axel Jantsch

Nicola Nicolici

IEEE Des. Test Comput., 2007

Embedded multi-detect ATPG and Its Effect on the Detection of Unmodeled Defects.

[BibT_eX]

[DOI]

Proceedings of the 2007 IEEE International Test Conference, 2007

Design and DfT of a high-speed area-efficient embedded asynchronous FIFO.

[BibT_eX]

[DOI]

Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

Test quality analysis and improvement for an embedded asynchronous FIFO.

[BibT_eX]

[DOI]

Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

2006

Conference Reports.

[BibT_eX]

[DOI]

IEEE Des. Test Comput., 2006

Wrapper Design for the Reuse of Networks-on-Chip as Test Access Mechanism.

[BibT_eX]

[DOI]

Proceedings of the 11th European Test Symposium, 2006

Hierarchy-aware and area-efficient test infrastructure design for core-based system chips.

[BibT_eX]

[DOI]

Anuja Sehgal

Proceedings of the Conference on Design, Automation and Test in Europe, 2006

2005

Optimal Interconnect ATPG Under a Ground-Bounce Constraint.

[BibT_eX]

[DOI]

Henk D. L. Hollmann

Bart Vermeulen

J. Electron. Test., 2005

Test scheduling for modular SOCs in an abort-on-fail environment.

[BibT_eX]

[DOI]

Proceedings of the 10th European Test Symposium, 2005

Challenges in Embedded Memory Design and Test.

[BibT_eX]

[DOI]

Proceedings of the 2005 Design, 2005

On-Chip Test Infrastructure Design for Optimal Multi-Site Testing of System Chips.

[BibT_eX]

[DOI]

Proceedings of the 2005 Design, 2005

IEEE Std 1500 Compliant Infrastructure forModular SOC Testing.

[BibT_eX]

[DOI]

Tom Waayers

Maurice Lousberg

Proceedings of the 14th Asian Test Symposium (ATS 2005), 2005

2004

Trends in Testing Integrated Circuits.

[BibT_eX]

[DOI]

Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004

IEEE P1500-Compliant Test Wrapper Design for Hierarchical Cores.

[BibT_eX]

[DOI]

Anuja Sehgal

Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004

Security vs. Test Quality: Can We Really Only Have One at a Time?

[BibT_eX]

[DOI]

Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004

User-constrained test architecture design for modular SOC testing.

[BibT_eX]

[DOI]

Proceedings of the 9th European Test Symposium, 2004

Test Infrastructure Design for the Nexperia? Home Platform PNX8550 System Chip.

[BibT_eX]

[DOI]

Proceedings of the 2004 Design, 2004

Infrastructure for modular SOC testing.

[BibT_eX]

[DOI]

Tom Waayers

Proceedings of the IEEE 2004 Custom Integrated Circuits Conference, 2004

2003

SOC test architecture design for efficient utilization of test bandwidth.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2003

Efficient test access mechanism optimization for system-on-chip.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003

Test Access Mechanism Optimization, Test Scheduling, and Tester Data Volume Reduction for System-on-Chip.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2003

A Test Time Reduction Algorithm for Test Architecture Design for Core-Based System Chips.

[BibT_eX]

[DOI]

J. Electron. Test., 2003

Minimizing Pattern Count for Interconnect Test under a Ground Bounce Constraint.

[BibT_eX]

[DOI]

IEEE Des. Test Comput., 2003

Yield analysis for repairable embedded memories.

[BibT_eX]

[DOI]

Proceedings of the 8th European Test Workshop, 2003

Control-aware test architecture design for modular SOC testing.

[BibT_eX]

[DOI]

Proceedings of the 8th European Test Workshop, 2003

Creating Value Through Test.

[BibT_eX]

[DOI]

Proceedings of the 2003 Design, 2003

Layout-Driven SOC Test Architecture Design for Test Time and Wire Length Minimization.

[BibT_eX]

[DOI]

Proceedings of the 2003 Design, 2003

2002

On IEEE P1500's Standard for Embedded Core Test.

[BibT_eX]

[DOI]

J. Electron. Test., 2002

The Role of Test Protocols in Automated Test Generation for Embedded-Core-Based System ICs.

[BibT_eX]

[DOI]

J. Electron. Test., 2002

Test Wrapper and Test Access Mechanism Co-Optimization for System-on-Chip.

[BibT_eX]

[DOI]

J. Electron. Test., 2002

How Useful are the ITC 02 SoC Test Benchmarks?

[BibT_eX]

IEEE Des. Test Comput., 2002

On Using Rectangle Packing for SOC Wrapper/TAM Co-Optimization.

[BibT_eX]

[DOI]

Proceedings of the 20th IEEE VLSI Test Symposium (VTS 2002), Without Testing It's a Gamble, 28 April, 2002

Cluster-Based Test Architecture Design for System-on-Chip.

[BibT_eX]

[DOI]

Proceedings of the 20th IEEE VLSI Test Symposium (VTS 2002), Without Testing It's a Gamble, 28 April, 2002

A Set of Benchmarks fo Modular Testing of SOCs.

[BibT_eX]

[DOI]

Proceedings of the Proceedings IEEE International Test Conference 2002, 2002

Test Resource Optimization for Multi-Site Testing of SOCs Under ATE Memory Depth Constraints.

[BibT_eX]

[DOI]

Proceedings of the Proceedings IEEE International Test Conference 2002, 2002

Effective and Efficient Test Architecture Design for SOCs.

[BibT_eX]

[DOI]

Proceedings of the Proceedings IEEE International Test Conference 2002, 2002

A novel test time reduction algorithm for test architecture design for core-based system chips.

[BibT_eX]

[DOI]

Proceedings of the 7th European Test Workshop, 2002

Efficient Wrapper/TAM Co-Optimization for Large SOCs.

[BibT_eX]

[DOI]

Proceedings of the 2002 Design, 2002

Wrapper/TAM co-optimization, constraint-driven test scheduling, and tester data volume reduction for SOCs.

[BibT_eX]

[DOI]

Proceedings of the 39th Design Automation Conference, 2002

Recent Advances in Test Planning for Modular Testing of Core-Based SOCs.

[BibT_eX]

[DOI]

Proceedings of the 11th Asian Test Symposium (ATS 2002), 18-20 November 2002, Guam, USA, 2002

2001

Application of Deterministic Logic BIST on Industrial Circuits.

[BibT_eX]

[DOI]

Gundolf Kiefer

Harald P. E. Vranken

Hans-Joachim Wunderlich

J. Electron. Test., 2001

Testing Embedded Core-Based System Chips.

[BibT_eX]

Proceedings of the 2nd Latin American Test Workshop, 2001

An Industrial Approach to Core-Based System Chip Testing.

[BibT_eX]

Proceedings of the SOC Design Methodologies, 2001

2000

Wrapper design for embedded core test.

[BibT_eX]

[DOI]

Proceedings of the Proceedings IEEE International Test Conference 2000, 2000

On using IEEE P1500 SECT for test plug-n-play.

[BibT_eX]

[DOI]

Rohit Kapur

Proceedings of the Proceedings IEEE International Test Conference 2000, 2000

System chip test: how will it impact your design?

[BibT_eX]

[DOI]

Proceedings of the 37th Conference on Design Automation, 2000

1999

Testing Embedded-Core-Based System Chips.

[BibT_eX]

[DOI]

Sujit Dey

Computer, 1999

Challenges in testing core-based system ICs.

[BibT_eX]

[DOI]

IEEE Commun. Mag., 1999

Towards a standard for embedded core test: an example.

[BibT_eX]

[DOI]

Proceedings of the Proceedings IEEE International Test Conference 1999, 1999

The role of test protocols in testing embedded-core-based system ICs.

[BibT_eX]

[DOI]

Maurice Lousberg

Proceedings of the 4th European Test Workshop, 1999

1998

A structured and scalable mechanism for test access to embedded reusable cores.

[BibT_eX]

[DOI]

Robert G. J. Arendsen

Proceedings of the Proceedings IEEE International Test Conference 1998, 1998

Scan chain design for test time reduction in core-based ICs.

[BibT_eX]

[DOI]

Joep Aerts