Jayashree Saxena

According to our database1, Jayashree Saxena authored at least 18 papers between 1992 and 2009.

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Bibliography

2009
Multidimensional Test Escape Rate Modeling.
IEEE Des. Test Comput., 2009

2008
Low Power Test for Nanometer System-on-Chips (SoCs).
J. Low Power Electron., 2008

Modeling Test Escape Rate as a Function of Multiple Coverages.
Proceedings of the 2008 IEEE International Test Conference, 2008

2004
Minimizing Power Consumption in Scan Testing: Pattern Generation and DFT Techniques.
Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004

2003
A Case Study of IR-Drop in Structured At-Speed Testing.
Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003

2002
Scan-Based Transition Fault Testing - Implementation and Low Cost Test Challenges .
Proceedings of the Proceedings IEEE International Test Conference 2002, 2002

2001
An analysis of power reduction techniques in scan testing.
Proceedings of the Proceedings IEEE International Test Conference 2001, Baltimore, MD, USA, 30 October, 2001

2000
Computer-aided fault to defect mapping (CAFDM) for defect diagnosis.
Proceedings of the Proceedings IEEE International Test Conference 2000, 2000

An empirical study on the effects of test type ordering on overall test efficiency.
Proceedings of the Proceedings IEEE International Test Conference 2000, 2000

1998
On applying non-classical defect models to automated diagnosis.
Proceedings of the Proceedings IEEE International Test Conference 1998, 1998

IC diagnosis: preventing wars and war stories.
Proceedings of the Proceedings IEEE International Test Conference 1998, 1998

1997
Automated Diagnosis in Testing and Failure Analysis.
IEEE Des. Test Comput., 1997

Bridging Fault Diagnosis in the Absence of Physical Information.
Proceedings of the Proceedings IEEE International Test Conference 1997, 1997

1996
Integrating Automated Diagnosis into the Testing and Failure Analysis Operations.
Proceedings of the Proceedings IEEE International Test Conference 1996, 1996

1995
A novel scheme to reduce test application time in circuits with full scan.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995

1993
A Method to Derive Compact Test Sets for Path Delay Faults in Combinational Circuits.
Proceedings of the Proceedings IEEE International Test Conference 1993, Designing, Testing, and Diagnostics, 1993

Desgin for Testability of Asynchronous Sequential Circuits.
Proceedings of the Proceedings 1993 International Conference on Computer Design: VLSI in Computers & Processors, 1993

1992
A design for testability scheme to reduce test application time in full scan.
Proceedings of the 10th IEEE VLSI Test Symposium (VTS'92), 1992


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