Lei Gong

Orcid: 0000-0002-8391-5526

Affiliations:
  • University of Science and Technology of China, Hefei, China


According to our database1, Lei Gong authored at least 105 papers between 2017 and 2026.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book  In proceedings  Article  PhD thesis  Dataset  Other 

Links

Online presence:

On csauthors.net:

Bibliography

2026
LORA: A Latency-Oriented Recurrent Architecture for Large Language Model on Multi-FPGA Platform With Communication Optimization.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., July, 2026

UniSparTa: A Unified Sparse Tensor Program Tuning Framework.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., July, 2026

Scheduling Cause-Effect Chains without Timing Anomalies in End-to-End Latency.
CoRR, April, 2026

TETRIS: A Novel FPGA Virtualization Framework for Fine-grained Sharing via Hierarchical Reconfiguration.
ACM Trans. Reconfigurable Technol. Syst., March, 2026

Hermes: A Unified High-Performance NTT Architecture with Hybrid Dataflow.
CoRR, March, 2026

MoE-Sched: Enabling Efficient FPGA Deployment of Mixture-of-Experts Vision Transformers via Coordinated Scheduling.
IEEE Trans. Very Large Scale Integr. Syst., January, 2026

UniCoX: A Unified Cost Model for Tensorized Program Tuning Across Ubiquitous Accelerators.
IEEE Trans. Computers, January, 2026

FG-KD: A Novel Forward Gradient-Based Framework for Teacher Knowledge Augmentation.
IEEE Trans. Artif. Intell., January, 2026

A Timing-Anomaly Free Dynamic Scheduling on Heterogeneous Systems.
CoRR, January, 2026

Reducing End-to-End Latency of Cause-Effect Chains with Shared Cache Analysis.
CoRR, January, 2026

Crystal-KV: Efficient KV Cache Management for Chain-of-Thought LLMs via Answer-First Principle.
CoRR, January, 2026

UDP: A Universal DSP Packing Framework for Low-bitwidth MAC Acceleration on FPGAs.
Proceedings of the 2026 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2026

CloserToMe: A Unified Framework for Accurate and Transferable Latency Prediction Across Heterogeneous Devices.
Proceedings of the Fortieth AAAI Conference on Artificial Intelligence, 2026

2025
ActionFlow: A Pipelined Action Acceleration for Vision Language Models on Edge.
CoRR, December, 2025

QLlama: An FPGA-Based Microscaling Quantization Accelerator for Energy-Efficient Llama2 Inference.
IEEE Embed. Syst. Lett., October, 2025

Advancing Neuromorphic Architecture Toward Emerging Spiking Neural Network on FPGA.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., September, 2025

Uncertainty-Aware Self-Knowledge Distillation.
IEEE Trans. Circuits Syst. Video Technol., May, 2025

Hardware Accelerated Vision Transformer via Heterogeneous Architecture Design and Adaptive Dataflow Mapping.
IEEE Trans. Computers, April, 2025

Knowledge Probabilization in Ensemble Distillation: Improving Accuracy and Uncertainty Quantification for Object Detectors.
IEEE Trans. Artif. Intell., January, 2025

Optimizing utilization in logical execution time system with preserved externally-observable timed I/O semantics.
J. Syst. Archit., 2025

Work-in-Progress: A Timing-Anomaly Free Dynamic Scheduling on Heterogeneous Systems.
Proceedings of the IEEE Real-Time Systems Symposium, 2025

TSI: A Time-Semantic Instruction Set for Deterministic Data-Flow Execution in Real-Time Embedded Systems.
Proceedings of the IEEE Real-Time Systems Symposium, 2025

UbiMoE: A Ubiquitous Mixture-of-Experts Vision Transformer Accelerator With Hybrid Computation Pattern on FPGA.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2025

ResDDQN-FPGA: A Reinforcement Learning Framework for Dynamic and Efficient Control in Resonant DC-DC Converters.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2025

Automated FPGA Accelerator Generation Framework for Transformers with Dataflow Optimization.
Proceedings of the 54th International Conference on Parallel Processing, 2025

Ph.D. Project: A Novel Compilation-Based Approach for Generating Sparse Tensor Accelerators.
Proceedings of the 33rd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2025

CoQMoE: Co-Designed Quantization and Computation Orchestration for Mixture-of-Experts Vision Transformer on FPGA.
Proceedings of the Euro-Par 2025: Parallel Processing, 2025

An Efficient Bit-level Sparse MAC-accelerated Architecture with SW/HW Co-design on FPGA.
Proceedings of the 62nd ACM/IEEE Design Automation Conference, 2025

Late Breaking Results: A Fast Nearest Neighbor Search Acceleration for 3D Point Cloud.
Proceedings of the 62nd ACM/IEEE Design Automation Conference, 2025

UniCoS: A Unified Neural and Accelerator Co-Search Framework for CNNs and ViTs.
Proceedings of the 62nd ACM/IEEE Design Automation Conference, 2025

Late Breaking Results: Source-Aware Adaptive Cache Management for CXL-enabled Disaggregated Memory Sharing.
Proceedings of the 62nd ACM/IEEE Design Automation Conference, 2025

Hermes: An FPGA-based NTT Accelerator Supporting Various Lengths for HHE.
Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis, 2025

Optimizing the Execution Core for Value Prediction in Superscalar Processors.
Proceedings of the IEEE International Conference on Cluster Computing, 2025

A similarity-aware MOE-based method for optimizing tensor programs across diverse GPUs.
Proceedings of the IEEE International Conference on Cluster Computing, 2025

2024
Enhancing HLS Performance Prediction on FPGAs Through Multimodal Representation Learning.
IEEE Embed. Syst. Lett., December, 2024

FlexBCM: Hybrid Block-Circulant Neural Network and Accelerator Co-Search on FPGAs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., November, 2024

Unleashing Network/Accelerator Co-Exploration Potential on FPGAs: A Deeper Joint Search.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., October, 2024

Enhancing Graph Random Walk Acceleration via Efficient Dataflow and Hybrid Memory Architecture.
IEEE Trans. Computers, March, 2024

PriorNet: A Novel Lightweight Network with Multidimensional Interactive Attention for Efficient Image Dehazing.
CoRR, 2024

MFNAS: Multi-fidelity Exploration in Neural Architecture Search with Stable Zero-Shot Proxy.
Proceedings of the PRICAI 2024: Trends in Artificial Intelligence, 2024

UniCoMo: A Unified Learning-Based Cost Model for Tensorized Program Tuning.
Proceedings of the 42nd IEEE International Conference on Computer Design, 2024

AutoSparse: A Source-to-Source Format and Schedule Auto- Tuning Framework for Sparse Tensor Program.
Proceedings of the 42nd IEEE International Conference on Computer Design, 2024

Enhancing Long Sequence Input Processing in FPGA-Based Transformer Accelerators through Attention Fusion.
Proceedings of the Great Lakes Symposium on VLSI 2024, 2024

FlexWalker: An Efficient Multi-Objective Design Space Exploration Framework for HLS Design.
Proceedings of the 34th International Conference on Field-Programmable Logic and Applications, 2024

LORA: A Latency-Oriented Recurrent Architecture for GPT Model on Multi-FPGA Platform with Communication Optimization.
Proceedings of the 34th International Conference on Field-Programmable Logic and Applications, 2024

SoGraph: A State-Aware Architecture for Out-of-Memory Graph Processing on HBM-Equipped FPGAs.
Proceedings of the 34th International Conference on Field-Programmable Logic and Applications, 2024

Beyond Training: A Zero-Shot Framework to Neural Architecture and Accelerator Co-Exploration.
Proceedings of the IEEE International Conference on Cluster Computing, 2024

2023
Algorithm/Hardware Co-Optimization for Sparsity-Aware SpMM Acceleration of GNNs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., December, 2023

Enabling Fast and Memory-Efficient Acceleration for Pattern Matching Workloads: The Lightweight Automata Processing Engine.
IEEE Trans. Computers, April, 2023

NeuralMAE: Data-Efficient Neural Architecture Predictor with Masked Autoencoder.
Proceedings of the Pattern Recognition and Computer Vision - 6th Chinese Conference, 2023

hAP: A Spatial-von Neumann Heterogeneous Automata Processor with Optimized Resource and IO Overhead on FPGA.
Proceedings of the 2023 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2023

DataMaster: A GNN-based Data Type Optimizer for Dataflow Design in FPGA.
Proceedings of the 31st IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2023

Enabling Elastic Resource Management in Cloud FPGAs via A Multi-layer Collaborative Approach.
Proceedings of the 31st IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2023

NAF: Deeper Network/Accelerator Co-Exploration for Customizing CNNs on FPGA.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

FastRW: A Dataflow-Efficient and Memory-Aware Accelerator for Graph Random Walk on FPGAs.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

Work-in-Progress: NAPMAE: Generalized Data-Efficient Neural Architecture Predictor with Masked Autoencoder.
Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis, 2023

Sparse-HeteroCL: From Sparse Tensor Algebra to Highly Customized Accelerators on FPGAs.
Proceedings of the 23rd IEEE/ACM International Symposium on Cluster, 2023

A flexible dataflow CNN accelerator on FPGA.
Proceedings of the 23rd IEEE/ACM International Symposium on Cluster, 2023

2022
ViA: A Novel Vision-Transformer Accelerator Based on FPGA.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

OctCNN: A High Throughput FPGA Accelerator for CNNs Using Octave Convolution Algorithm.
IEEE Trans. Computers, 2022

Conv-inheritance: A hardware-efficient method to compress convolutional neural networks for edge applications.
Neurocomputing, 2022

Multi-clusters: An Efficient Design Paradigm of NN Accelerator Architecture Based on FPGA.
Proceedings of the Network and Parallel Computing, 2022

WGeod: A General and Efficient FPGA Accelerator for Object Detection.
Proceedings of the IEEE Intl Conf on Parallel & Distributed Processing with Applications, 2022

SDMA: An Efficient and Flexible Sparse-Dense Matrix-Multiplication Architecture for GNNs.
Proceedings of the 32nd International Conference on Field-Programmable Logic and Applications, 2022

Work-in-Progress: BloCirNN: An Efficient Software/hardware Codesign Approach for Neural Network Accelerators with Block-Circulant Matrix.
Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis, 2022

Work-in-Progress: HeteroRW: A Generalized and Efficient Framework for Random Walks in Graph Analysis.
Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis, 2022

2021
SOLAR: Services-Oriented Deep Learning Architectures-Deep Learning as a Service.
IEEE Trans. Serv. Comput., 2021

Improving HW/SW Adaptability for Accelerating CNNs on FPGAs Through A Dynamic/Static Co-Reconfiguration Approach.
IEEE Trans. Parallel Distributed Syst., 2021

GenSeq+: A Scalable High-Performance Accelerator for Genome Sequencing.
IEEE ACM Trans. Comput. Biol. Bioinform., 2021

Tinker: A Middleware for Deploying Multiple NN-Based Applications on a Single Machine.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021

An FPGA Based Accelerator for Clustering Algorithms With Custom Instructions.
IEEE Trans. Computers, 2021

Neural Network Instruction Set Extension and Code Mapping Mechanism.
Int. J. Softw. Informatics, 2021

FEAS: A Faster Event-driven Accelerator Supporting Inhibitory Spiking Neural Network.
Proceedings of the 12th International Symposium on Parallel Architectures, 2021

Vapor: A GPU Sharing Scheduler with Communication and Computation Pipeline for Distributed Deep Learning.
Proceedings of the 2021 IEEE Intl Conf on Parallel & Distributed Processing with Applications, Big Data & Cloud Computing, Sustainable Computing & Communications, Social Computing & Networking (ISPA/BDCloud/SocialCom/SustainCom), New York City, NY, USA, September 30, 2021

UH-JLS: A Parallel Ultra-High Throughput JPEG-LS Encoding Architecture for Lossless Image Compression.
Proceedings of the 39th IEEE International Conference on Computer Design, 2021

LAP: A Lightweight Automata Processor for Pattern Matching Tasks.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

2020
A Ubiquitous Machine Learning Accelerator With Automatic Parallelization on FPGA.
IEEE Trans. Parallel Distributed Syst., 2020

WinoNN: Optimizing FPGA-Based Convolutional Neural Network Accelerators Using Sparse Winograd Algorithm.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

WooKong: A Ubiquitous Accelerator for Recommendation Algorithms With Custom Instruction Sets on FPGA.
IEEE Trans. Computers, 2020

Chameleon: Image Style Transfer Based on Image Classification Networks.
Proceedings of the 22nd IEEE International Conference on High Performance Computing and Communications; 18th IEEE International Conference on Smart City; 6th IEEE International Conference on Data Science and Systems, 2020

ConvCloud: An Adaptive Convolutional Neural Network Accelerator on Cloud FPGAs.
Proceedings of the FPGA '20: The 2020 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2020

WiderFrame: An Automatic Customization Framework for Building CNN Accelerators on FPGAs: Work-in-Progress.
Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis, 2020

OctCNN: An Energy-Efficient FPGA Accelerator for CNNs using Octave Convolution Algorithm.
Proceedings of the IEEE International Conference on Cluster Computing, 2020

2019
FPNet: Customized Convolutional Neural Network for FPGA Platforms.
Proceedings of the International Conference on Field-Programmable Technology, 2019

Design Exploration of Multi-FPGAs for Accelerating Deep Learning.
Proceedings of the 2019 IEEE International Conference on Cluster Computing, 2019

RV-CNN: Flexible and Efficient Instruction Set for CNNs Based on RISC-V Processors.
Proceedings of the Advanced Parallel Processing Technologies, 2019

2018
MALOC: A Fully Pipelined FPGA Accelerator for Convolutional Neural Networks With All Layers Mapped on Chip.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

UniCNN: A Pipelined Accelerator Towards Uniformed Computing for CNNs.
Int. J. Parallel Program., 2018

SparseNN: A Performance-Efficient Accelerator for Large-Scale Sparse Neural Networks.
Int. J. Parallel Program., 2018

Domino: Graph Processing Services on Energy-Efficient Hardware Accelerator.
Proceedings of the 2018 IEEE International Conference on Web Services, 2018

Domino: An Asynchronous and Energy-efficient Accelerator for Graph Processing: (Abstract Only).
Proceedings of the 2018 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2018

Furion: alleviating overheads for deep learning framework on single machine (work-in-progress).
Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis, 2018

2017
DLAU: A Scalable Deep Learning Accelerator Unit on FPGA.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017

Reconfigurable Hardware Accelerators: Opportunities, Trends, and Challenges.
CoRR, 2017

Implementation and Optimization of the Accelerator Based on FPGA Hardware for LSTM Network.
Proceedings of the 2017 IEEE International Symposium on Parallel and Distributed Processing with Applications and 2017 IEEE International Conference on Ubiquitous Computing and Communications (ISPA/IUCC), 2017

A High-Performance Accelerator for Large-Scale Convolutional Neural Networks.
Proceedings of the 2017 IEEE International Symposium on Parallel and Distributed Processing with Applications and 2017 IEEE International Conference on Ubiquitous Computing and Communications (ISPA/IUCC), 2017

Evaluation and Trade-offs of Graph Processing for Cloud Services.
Proceedings of the 2017 IEEE International Conference on Web Services, 2017

xFilter: A Temporal Locality Accelerator for Intrusion Detection System Services.
Proceedings of the 2017 IEEE International Conference on Web Services, 2017

GenServ: Genome Sequencing Services on Scalable Energy Efficient Accelerators.
Proceedings of the 2017 IEEE International Conference on Web Services, 2017

FPGA Based Big Data Accelerator Design in Teaching Computer Architecture and Organization.
Proceedings of the Cyber Physical Systems. Design, Modeling, and Evaluation, 2017

A power-efficient and high performance FPGA accelerator for convolutional neural networks: work-in-progress.
Proceedings of the Twelfth IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis Companion, 2017

A Power-Efficient Accelerator Based on FPGAs for LSTM Network.
Proceedings of the 2017 IEEE International Conference on Cluster Computing, 2017

OmniGraph: A Scalable Hardware Accelerator for Graph Processing.
Proceedings of the 2017 IEEE International Conference on Cluster Computing, 2017

A Power-Efficient Accelerator for Convolutional Neural Networks.
Proceedings of the 2017 IEEE International Conference on Cluster Computing, 2017

A high-performance FPGA accelerator for sparse neural networks: work-in-progress.
Proceedings of the 2017 International Conference on Compilers, 2017


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