Qianyu Cheng
Orcid: 0000-0001-8321-6920
According to our database1,
Qianyu Cheng authored at least 23 papers
between 2021 and 2026.
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Bibliography
2026
LORA: A Latency-Oriented Recurrent Architecture for Large Language Model on Multi-FPGA Platform With Communication Optimization.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., July, 2026
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., July, 2026
CoRR, March, 2026
Generative Engine Optimization: A VLM and Agent Framework for Pinterest Acquisition Growth.
CoRR, February, 2026
UniCoX: A Unified Cost Model for Tensorized Program Tuning Across Ubiquitous Accelerators.
IEEE Trans. Computers, January, 2026
Proceedings of the Fortieth AAAI Conference on Artificial Intelligence, 2026
2025
CoRR, December, 2025
IEEE Embed. Syst. Lett., October, 2025
PinLanding: Content-First Keyword Landing Page Generation via Multi-Modal AI for Web-Scale Discovery.
CoRR, March, 2025
Spectral Enhanced Tuning: An Efficient Plug-and-Play Framework for Frequency-Aware Dehazing.
Proceedings of the IEEE International Conference on Multimedia and Expo, 2025
Late Breaking Results: A Fast Nearest Neighbor Search Acceleration for 3D Point Cloud.
Proceedings of the 62nd ACM/IEEE Design Automation Conference, 2025
Late Breaking Results: Source-Aware Adaptive Cache Management for CXL-enabled Disaggregated Memory Sharing.
Proceedings of the 62nd ACM/IEEE Design Automation Conference, 2025
Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis, 2025
2024
Exploring the Spatiotemporal Effects of the Built Environment on the Nonlinear Impacts of Metro Ridership: Evidence from Xi'an, China.
ISPRS Int. J. Geo Inf., February, 2024
A genetic optimisation model for energy conservation of circulating water pump station with variable speed pumps.
Int. J. Bio Inspired Comput., 2024
Proceedings of the 42nd IEEE International Conference on Computer Design, 2024
AutoSparse: A Source-to-Source Format and Schedule Auto- Tuning Framework for Sparse Tensor Program.
Proceedings of the 42nd IEEE International Conference on Computer Design, 2024
LORA: A Latency-Oriented Recurrent Architecture for GPT Model on Multi-FPGA Platform with Communication Optimization.
Proceedings of the 34th International Conference on Field-Programmable Logic and Applications, 2024
SoGraph: A State-Aware Architecture for Out-of-Memory Graph Processing on HBM-Equipped FPGAs.
Proceedings of the 34th International Conference on Field-Programmable Logic and Applications, 2024
Ph.D. Project: Optimizing the Data Traffic for Large Graph Processing on FPGA via a Stateful Approach.
Proceedings of the 32nd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2024
2023
Aggregation Mechanisms in Federated Learning for Enhancing Robotic Visual Obstacle Avoidance.
Proceedings of the 5th International Conference on Robotics, 2023
2021