Xu Cheng
Orcid: 0000-0002-0314-0178Affiliations:
- Fudan University, State Key Laboratory of ASIC and System, Shanghai, China
- Cypress Semiconductor Corporation, Ireland Design Centre, Ireland (2007 - 2009)
- University College Cork, Tyndall National Institute, Ireland (PhD 2007)
According to our database1,
Xu Cheng
authored at least 44 papers
between 2011 and 2024.
Collaborative distances:
Collaborative distances:
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Bibliography
2024
A 1.6 GS/s 42.6-dB SNDR Synthesis Friendly Time-Interleaved SAR ADC Using Metastability Detection and Escape Acceleration Technique.
IEEE Trans. Circuits Syst. II Express Briefs, April, 2024
SET Tolerable SRAM Hardened by DMR Circuit With Feedback-Split-Gate Voter and High-Speed Hierarchical Structure.
IEEE Trans. Circuits Syst. II Express Briefs, March, 2024
An Energy-Efficient BNN Accelerator With Two-Stage Value Prediction for Sparse-Edge Gesture Recognition.
IEEE Trans. Circuits Syst. I Regul. Pap., January, 2024
2023
Dominant-Node Theory and Monitoring-Rescue Method for Eliminating Undesired Operating Points in the Self-Biased Reference Generators.
IEEE Trans. Circuits Syst. I Regul. Pap., December, 2023
DMBF: Design Metrics Balancing Framework for Soft-Error-Tolerant Digital Circuits Through Bayesian Optimization.
IEEE Trans. Circuits Syst. I Regul. Pap., October, 2023
A Non-Redundant Latch With Key-Node-Upset Obstacle of Beneficial Efficiency for Harsh Environments Applications.
IEEE Trans. Circuits Syst. I Regul. Pap., April, 2023
A foreground digital calibration algorithm for time-interleaved ADCs with low computational complexity.
Microelectron. J., 2023
A Self Bias-flip Piezoelectric Energy Harvester Array without External Energy Reservoirs achieving 488% Improvement with 4-Ratio Switched-PEH DC-DC Converter.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2023
2022
An Enhanced Start-up Circuit Eliminating All Trojan States in Self-biased Reference Generators.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
A Synthesis Friendly Dynamic Amplifier with Fuzzy-Logic Piecewise-Linear Calibration.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
A Cross Regulation Reduced Multi-Output and Multi-VCR Piezoelectric Energy Harvesting System Using Shared Capacitors.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
2021
General Efficient TMR for Combinational Circuit Hardening Against Soft Errors and Improved Multi-Objective Optimization Framework.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021
Radiation Hardened 12T SRAM With Crossbar-Based Peripheral Circuit in 28nm CMOS Technology.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021
A 28 nm, 397 μW real-time dynamic gesture recognition chip based on RISC-V processor.
Microelectron. J., 2021
Microelectron. J., 2021
A Synthesizable 0.0060mm<sup>2</sup> VCO-Based Delta Sigma Modulator with Digital Tri-level Feedback Scheme.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2021
A High-Efficient and Configurable Hardware Accelerator for Convolutional Neural Network.
Proceedings of the 14th IEEE International Conference on ASIC, 2021
Proceedings of the 14th IEEE International Conference on ASIC, 2021
2020
Radiation-Hardened 0.3-0.9-V Voltage-Scalable 14T SRAM and Peripheral Circuit in 28-nm Technology for Space Applications.
IEEE Trans. Very Large Scale Integr. Syst., 2020
VPQC: A Domain-Specific Vector Processor for Post-Quantum Cryptography Based on RISC-V Architecture.
IEEE Trans. Circuits Syst. I Regul. Pap., 2020
A Robust Hardened Latch Featuring Tolerance to Double-Node-Upset in 28nm CMOS for Spaceborne Application.
IEEE Trans. Circuits Syst. II Express Briefs, 2020
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
Exploring a Bayesian Optimization Framework Compatible with Digital Standard Flow for Soft-Error-Tolerant Circuit.
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020
2019
IEICE Electron. Express, 2019
2016
Bit-Interleaving-Enabled 8T SRAM With Shared Data-Aware Write and Reference-Based Sense Amplifier.
IEEE Trans. Circuits Syst. II Express Briefs, 2016
Subthreshold Level Shifter With Self-Controlled Current Limiter by Detecting Output Error.
IEEE Trans. Circuits Syst. II Express Briefs, 2016
Analysis and improvement of ramp gain error in single-ramp single-slope ADCs for CMOS image sensors.
Microelectron. J., 2016
2015
Design and Analysis of Highly Energy/Area-Efficient Multiported Register Files With Read Word-Line Sharing Strategy in 65-nm CMOS Process.
IEEE Trans. Very Large Scale Integr. Syst., 2015
IEICE Electron. Express, 2015
2014
IEEE Trans. Circuits Syst. I Regul. Pap., 2014
An area-efficient dual replica-bitline delay technique for process-variation-tolerant low voltage SRAM sense amplifier timing.
IEICE Electron. Express, 2014
2013
Microelectron. J., 2013
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013
A highly energy-efficient compressed sensing encoder with robust subthreshold clockless pipeline for wireless BANs.
Proceedings of the 2013 IEEE Biomedical Circuits and Systems Conference (BioCAS), Rotterdam, The Netherlands, October 31, 2013
Proceedings of the IEEE 10th International Conference on ASIC, 2013
An extensible and real-time compressive sensing reconstruction hardware for WBANs using OMP.
Proceedings of the IEEE 10th International Conference on ASIC, 2013
2012
IEICE Electron. Express, 2012
2011
Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011
Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011
A multi-mode 1-V DAC+filter in 65-nm CMOS for reconfigurable (GSM, TD-SCDMA and WCDMA) transmitters.
Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011
Modeling of a double-sampling switched-capacitor bandpass delta-sigma modulator for multi-standard applications.
Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011