Yan Li

Orcid: 0000-0002-8918-7320

Affiliations:

Fudan University, State Key Laboratory of ASIC and System, Shanghai, China

According to our database¹, Yan Li authored at least 11 papers between 2020 and 2026.

Collaborative distances:

Dijkstra number² of five.
Erdős number³ of four.

Timeline

Legend:

Book In proceedings Article PhD thesis Dataset Other

Bibliography

2026

Toward Exploring Fault-Tolerant Neural Architectures: A Hierarchical Codesign Optimization Framework.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., May, 2026

When High Reliability Meets Low Cost: Exploring Approximate-TMR via Efficient Multiobjective Optimization Frameworks.

[BibT_eX]

[DOI]

Yueming Hu

Yan Li

Xiaoyang Zeng

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., January, 2026

2024

Examining the role of tap cell in suppressing single event transient effect in 28-nm CMOS technology.

[BibT_eX]

[DOI]

Microelectron. J., January, 2024

Novel partial punch-through-stopper scheme for substrate leakage optimization of nanosheet field-effect transistors.

[BibT_eX]

[DOI]

Microelectron. J., January, 2024

2023

DMBF: Design Metrics Balancing Framework for Soft-Error-Tolerant Digital Circuits Through Bayesian Optimization.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., October, 2023

A Non-Redundant Latch With Key-Node-Upset Obstacle of Beneficial Efficiency for Harsh Environments Applications.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., April, 2023

2022

An Improved Multi-Objective Optimization Framework for Soft-Error Immune Circuits.

[BibT_eX]

[DOI]

Proceedings of the IEEE Asia Pacific Conference on Circuit and Systems, 2022

2021

General Efficient TMR for Combinational Circuit Hardening Against Soft Errors and Improved Multi-Objective Optimization Framework.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2021

TRIGON: A Single-phase-clocking Low Power Hardened Flip-Flop with Tolerance to Double-Node-Upset for Harsh Environments Applications.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

2020

A Robust Hardened Latch Featuring Tolerance to Double-Node-Upset in 28nm CMOS for Spaceborne Application.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2020

Exploring a Bayesian Optimization Framework Compatible with Digital Standard Flow for Soft-Error-Tolerant Circuit.

[BibT_eX]

[DOI]

Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

Yan Li

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Bibliography

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