Yan Li
Orcid: 0000-0002-8918-7320Affiliations:
- Fudan University, State Key Laboratory of ASIC and System, Shanghai, China
According to our database1,
Yan Li
authored at least 9 papers
between 2020 and 2024.
Collaborative distances:
Collaborative distances:
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Bibliography
2024
Examining the role of tap cell in suppressing single event transient effect in 28-nm CMOS technology.
Microelectron. J., January, 2024
Novel partial punch-through-stopper scheme for substrate leakage optimization of nanosheet field-effect transistors.
Microelectron. J., January, 2024
2023
DMBF: Design Metrics Balancing Framework for Soft-Error-Tolerant Digital Circuits Through Bayesian Optimization.
IEEE Trans. Circuits Syst. I Regul. Pap., October, 2023
A Non-Redundant Latch With Key-Node-Upset Obstacle of Beneficial Efficiency for Harsh Environments Applications.
IEEE Trans. Circuits Syst. I Regul. Pap., April, 2023
2022
Proceedings of the IEEE Asia Pacific Conference on Circuit and Systems, 2022
2021
General Efficient TMR for Combinational Circuit Hardening Against Soft Errors and Improved Multi-Objective Optimization Framework.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021
TRIGON: A Single-phase-clocking Low Power Hardened Flip-Flop with Tolerance to Double-Node-Upset for Harsh Environments Applications.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021
2020
A Robust Hardened Latch Featuring Tolerance to Double-Node-Upset in 28nm CMOS for Spaceborne Application.
IEEE Trans. Circuits Syst. II Express Briefs, 2020
Exploring a Bayesian Optimization Framework Compatible with Digital Standard Flow for Soft-Error-Tolerant Circuit.
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020