Ruzica Jevtic

According to our database, Ruzica Jevtic authored at least 22 papers between 2007 and 2022.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2022

Methodology for Complete Decorrelation of Power Supply EM Side-Channel Signal and Sensitive Data.

Ruzica Jevtic, Mariano García Otero

IEEE Trans. Circuits Syst. II Express Briefs, 2022

Side-channel Attack Countermeasure Based on Power Supply Modulation.

Ruzica Jevtic, Pablo Pérez-Tirador, Carmen Cabezaolias, Pablo Carnero, Gabriel Caffarena

Proceedings of the 30th European Signal Processing Conference, 2022

2021

EM Side-Channel Countermeasure for Switched-Capacitor DC-DC Converters Based on Amplitude Modulation.

Ruzica Jevtic, Marko Ylitolva, Clara Calonge, Martti Ojanen, Tero Säntti, Lauri Koskinen

IEEE Trans. Very Large Scale Integr. Syst., 2021

2018

Reconfigurable Switched Capacitor DC-DC Converter for Improved Security in IoT Devices.

Ruzica Jevtic, Marko Ylitolva, Lauri Koskinen

Proceedings of the 28th International Symposium on Power and Timing Modeling, 2018

2016

An Agile Approach to Building RISC-V Microprocessors.

Yunsup Lee, Andrew Waterman, Henry Cook, Brian Zimmer, Ben Keller, Alberto Puggelli, Jaehwa Kwak, Ruzica Jevtic, Stevo Bailey, Milovan Blagojevic, Pi-Feng Chiu, Rimas Avizienis, Brian C. Richards, Jonathan Bachrach, David A. Patterson, Elad Alon, Bora Nikolic, Krste Asanovic

IEEE Micro, 2016

A RISC-V Vector Processor With Simultaneous-Switching Switched-Capacitor DC-DC Converters in 28 nm FDSOI.

Brian Zimmer, Yunsup Lee, Alberto Puggelli, Jaehwa Kwak, Ruzica Jevtic, Ben Keller, Steven Bailey, Milovan Blagojevic, Pi-Feng Chiu, Hanh-Phuc Le, Po-Hung Chen, Nicholas Sutardja, Rimas Avizienis, Andrew Waterman, Brian C. Richards, Philippe Flatresse, Elad Alon, Krste Asanovic, Borivoje Nikolic

IEEE J. Solid State Circuits, 2016

2015

Per-Core DVFS With Switched-Capacitor Converters for Energy Efficiency in Manycore Processors.

Ruzica Jevtic, Hanh-Phuc Le, Milovan Blagojevic, Stevo Bailey, Krste Asanovic, Elad Alon, Borivoje Nikolic

IEEE Trans. Very Large Scale Integr. Syst., 2015

A RISC-V vector processor with tightly-integrated switched-capacitor DC-DC converters in 28nm FDSOI.

Brian Zimmer, Yunsup Lee, Alberto Puggelli, Jaehwa Kwak, Ruzica Jevtic, Ben Keller, Stevo Bailey, Milovan Blagojevic, Pi-Feng Chiu, Hanh-Phuc Le, Po-Hung Chen, Nicholas Sutardja, Rimas Avizienis, Andrew Waterman, Brian C. Richards, Philippe Flatresse, Elad Alon, Krste Asanovic, Borivoje Nikolic

Proceedings of the Symposium on VLSI Circuits, 2015

Fully integrated DC-DC converter and a 0.4V 32-bit CPU with timing-error prevention supplied from a prototype 1.55V Li-ion battery.

Matthew J. Turnquist, Markus Hiienkari, Jani Mäkipää, Ruzica Jevtic, Elina Pohjalainen, Tanja Kallio, Lauri Koskinen

Proceedings of the Symposium on VLSI Circuits, 2015

A MEMS microphone interface based on a CMOS LC oscillator and a digital sigma-delta modulator.

Fernando Cardes, Ruzica Jevtic, Luis Hernández, Andreas Wiesbauer, Dietmar Sträußnigg, Richard Gaggl

Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

Raven: A 28nm RISC-V vector processor with integrated switched-capacitor DC-DC converters and adaptive clocking.

Yunsup Lee, Brian Zimmer, Andrew Waterman, Alberto Puggelli, Jaehwa Kwak, Ruzica Jevtic, Ben Keller, Stevo Bailey, Milovan Blagojevic, Pi-Feng Chiu, Henry Cook, Rimas Avizienis, Brian C. Richards, Elad Alon, Borivoje Nikolic, Krste Asanovic

Proceedings of the 2015 IEEE Hot Chips 27 Symposium (HCS), 2015

2014

Binary Division Power Models for High-Level Power Estimation of FPGA-Based DSP Circuits.

Bojan Jovanovic, Ruzica Jevtic, Carlos Carreras

IEEE Trans. Ind. Informatics, 2014

Memory optimization in FPGA-accelerated scientific codes based on unstructured meshes.

Pablo Barrio, Carlos Carreras, Juan A. López, Óscar Robles, Ruzica Jevtic, Roberto Sierra

J. Syst. Archit., 2014

2012

A complete dynamic power estimation model for data-paths in FPGA DSP designs.

Ruzica Jevtic, Carlos Carreras

Integr., 2012

2011

Power Measurement Methodology for FPGA Devices.

Ruzica Jevtic, Carlos Carreras

IEEE Trans. Instrum. Meas., 2011

Technology Variability From a Design Perspective.

Borivoje Nikolic, Ji-Hoon Park, Jaehwa Kwak, Bastien Giraud, Zheng Guo, Liang-Teck Pang, Seng Oon Toh, Ruzica Jevtic, Kun Qian, Costas J. Spanos

IEEE Trans. Circuits Syst. I Regul. Pap., 2011

Power estimation of dividers implemented in FPGAs.

Ruzica Jevtic, Bojan Jovanovic, Carlos Carreras

Proceedings of the 21st ACM Great Lakes Symposium on VLSI 2010, 2011

2010

Power Estimation of Embedded Multiplier Blocks in FPGAs.

Ruzica Jevtic, Carlos Carreras

IEEE Trans. Very Large Scale Integr. Syst., 2010

2009

Floorplan-based FPGA interconnect power estimation in DSP circuits.

Ruzica Jevtic, Carlos Carreras, Vukasin Pejovic

Proceedings of the 11th International Workshop on System-Level Interconnect Prediction (SLIP 2009), 2009

2008

A Comparison of Approaches for High-Level Power Estimation of LUT-Based DSP Components.

Ruzica Jevtic, Carlos Carreras, Domenik Helms

Proceedings of the ReConFig'08: 2008 International Conference on Reconfigurable Computing and FPGAs, 2008

Analytical High-Level Power Model for LUT-Based Components.

Ruzica Jevtic, Carlos Carreras

Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2008

2007

Switching Activity Models for Power Estimation in FPGA Multipliers.

Ruzica Jevtic, Carlos Carreras, Gabriel Caffarena

Proceedings of the Reconfigurable Computing: Architectures, 2007