Mahipal Dargupally
Orcid: 0000-0001-5640-7342
According to our database1,
Mahipal Dargupally
authored at least 5 papers
between 2023 and 2024.
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Bibliography
2024
Switching Activity Factor-Based ECSM Characterization (SAFE): A Novel Technique for Aging-Aware Static Timing Analysis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., December, 2024
2023
Aging-Aware Timing Model of CMOS Inverter: Path Level Timing Performance and Its Impact on the Logical Effort.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023
Beyond SPICE Simulation: A Novel Variability-Aware STA Methodology for Digital Timing Closure.
Proceedings of the 19th International Conference on Synthesis, 2023
ABB Assisted Area Efficient Vernier Delay Line Time-to-Digital Converter for Low Voltage Applications.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2023
An Efficient Standard Cell Design Methodology by Exploiting Body Biasing and Poly Biasing in FDSOI for NTV Regime.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2023