Khoirom Johnson Singh
Orcid: 0000-0002-3013-3571
According to our database1,
Khoirom Johnson Singh
authored at least 7 papers
between 2021 and 2024.
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Bibliography
2024
Switching Activity Factor-Based ECSM Characterization (SAFE): A Novel Technique for Aging-Aware Static Timing Analysis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., December, 2024
2023
Negative capacitance gate stack and Landau FET-based voltage amplifiers and circuits: Impact of ferroelectric thickness and domain variations.
Microelectron. J., December, 2023
Aging-Aware Timing Model of CMOS Inverter: Path Level Timing Performance and Its Impact on the Logical Effort.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023
Beyond SPICE Simulation: A Novel Variability-Aware STA Methodology for Digital Timing Closure.
Proceedings of the 19th International Conference on Synthesis, 2023
An Efficient Standard Cell Design Methodology by Exploiting Body Biasing and Poly Biasing in FDSOI for NTV Regime.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2023
2022
Significance of Organic Ferroelectric in Harnessing Transient Negative Capacitance Effect at Low Voltage Over Oxide Ferroelectric.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
2021
Harnessing Maximum Negative Capacitance Signature Voltage Window in P(VDF-TrFE) Gate Stack.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021