Venkatraman Ramakrishnan

According to our database, Venkatraman Ramakrishnan authored at least 4 papers between 2021 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of five.

2024

Switching Activity Factor-Based ECSM Characterization (SAFE): A Novel Technique for Aging-Aware Static Timing Analysis.

Lomash Chandra Acharya, Arvind K. Sharma, Neeraj Mishra, Khoirom Johnson Singh, Mahipal Dargupally, Neha Gupta, Nayakanti Sai Shabarish, Ajoy Mandal, Venkatraman Ramakrishnan, Sudeb Dasgupta, Anand Bulusu

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., December, 2024

2023

Aging-Aware Timing Model of CMOS Inverter: Path Level Timing Performance and Its Impact on the Logical Effort.

Lomash Chandra Acharya, Arvind Kumar Sharma, Neeraj Mishra, Khoirom Johnson Singh, Mahipal Dargupally, Nayakanti Sai Shabarish, Ajoy Mandal, Venkatraman Ramakrishnan, Sudeb Dasgupta, Anand Bulusu

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023

Beyond SPICE Simulation: A Novel Variability-Aware STA Methodology for Digital Timing Closure.

Lomash Chandra Acharya, Anubhav Kumar, Khoirom Johnson Singh, Neha Gupta, Nayakanti Sai Shabarish, Neeraj Mishra, Mahipal Dargupally, Arvind Kumar Sharma, Venkatraman Ramakrishnan, Ajoy Mandal, Sudeb Dasgupta, Anand Bulusu

Proceedings of the 19th International Conference on Synthesis, 2023

2021

Variation Aware Timing Model of CMOS Inverter for an Efficient ECSM Characterization.

Lomash Chandra Acharya, Arvind Kumar Sharma, Venkatraman Ramakrishnan, Ajoy Mandal, Sudeb Dasgupta, Anand Bulusu

Proceedings of the 22nd International Symposium on Quality Electronic Design, 2021