Marco Bucci

According to our database1, Marco Bucci authored at least 25 papers between 1988 and 2016.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2016
A Fully-Digital Chaos-Based Random Bit Generator.
Proceedings of the New Codebreakers, 2016

2012
A Flip-Flop for the DPA Resistant Three-Phase Dual-Rail Pre-Charge Logic Family.
IEEE Trans. VLSI Syst., 2012

2011
Delay-Based Dual-Rail Precharge Logic.
IEEE Trans. VLSI Syst., 2011

2009
Delay-based dual-rail pre-charge logic.
Proceedings of the 16th IEEE International Conference on Electronics, 2009

2008
Fully Digital Random Bit Generators for Cryptographic Applications.
IEEE Trans. on Circuits and Systems, 2008

Enhancing power analysis attacks against cryptographic devices.
IET Circuits, Devices & Systems, 2008

Differential Capacitance Analysis.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2008

A Low Leakage Non-Volatile Memory Voltage Pulse Generator for RFID Applications.
Proceedings of the 11th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2008), 2008

2007
A Dynamic and Differential CMOS Lookup Table with Data-Independent Power Consumption for Cryptographic Applications on Chip Cards.
IEEE Trans. Dependable Sec. Comput., 2007

Testing power-analysis attack susceptibility in register-transfer level designs.
IET Information Security, 2007

A Testable Random Bit Generator Based on a High Resolution Phase Noise Detection.
Proceedings of the 10th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2007), 2007

2006
A novel concept for stateless random bit generators in cryptographic applications.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Enhancing power analysis attacks against cryptographic devices.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

A Leakage-based Random Bit Generator with On-line Fault Detection.
Proceedings of the 9th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2006), 2006

Three-Phase Dual-Rail Pre-charge Logic.
Proceedings of the Cryptographic Hardware and Embedded Systems, 2006

2005
Random Bit Generator.
Proceedings of the Encyclopedia of Cryptography and Security, 2005

A countermeasure against differential power analysis based on random delay insertion.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Design of Testable Random Bit Generators.
Proceedings of the Cryptographic Hardware and Embedded Systems - CHES 2005, 7th International Workshop, Edinburgh, UK, August 29, 2005

2004
A Power Consumption Randomization Countermeasure for DPA-Resistant Cryptographic Processors.
Proceedings of the Integrated Circuit and System Design, 2004

An Offset-Compensated Oscillator-Based Random Bit Source for Security Applications.
Proceedings of the Cryptographic Hardware and Embedded Systems, 2004

2003
A High-Speed Oscillator-Based Truly Random Number Source for Cryptographic Applications on a Smart Card IC.
IEEE Trans. Computers, 2003

A charge injection based CMOS charge-pump.
Proceedings of the 2003 10th IEEE International Conference on Electronics, 2003

2001
Supplemental Cryptographic Hardware for Smart Cards.
IEEE Micro, 2001

1999
A Design of Reliable True Random Number Generator for Cryptographic Applications.
Proceedings of the Cryptographic Hardware and Embedded Systems, 1999

1988
Fast Serial-Parallel Multipliers.
Proceedings of the Applied Algebra, 1988


  Loading...