Alessandro Trifiletti
Orcid: 0000-0001-6231-4273
According to our database1,
Alessandro Trifiletti
authored at least 167 papers
between 1998 and 2024.
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Bibliography
2024
Sensors, March, 2024
2023
Int. J. Circuit Theory Appl., November, 2023
High-Accuracy Low-Cost Generalized Complex Pruned Volterra Models for Nonlinear Calibration.
IEEE Trans. Circuits Syst. I Regul. Pap., September, 2023
A body-driven rail-to-rail 0.3 V operational transconductance amplifier exploiting current gain stages.
Int. J. Circuit Theory Appl., May, 2023
IEEE Access, 2023
A 0.3V Rail-to-Rail Three-Stage OTA With High DC Gain and Improved Robustness to PVT Variations.
IEEE Access, 2023
A Novel Parallel Digitizer With a Pulseless Mixing-Filtering-Processing Architecture and Its Implementation in a SiGe HBT Technology at 40GS/s.
IEEE Access, 2023
Proceedings of the 18th Conference on Ph.D Research in Microelectronics and Electronics, 2023
Proceedings of the 18th Conference on Ph.D Research in Microelectronics and Electronics, 2023
A 2.5 GHz, 0.6 V Body Driven Dynamic Comparator Exploiting Charge Pump Based Dynamic Biasing.
Proceedings of the 18th Conference on Ph.D Research in Microelectronics and Electronics, 2023
Proceedings of the International Workshop on Biomedical Applications, 2023
2022
IEEE Trans. Instrum. Meas., 2022
A SiGe HBT 6th-Order 10 GHz Inductor-Less Anti-Aliasing Low-Pass Filter for High-Speed ATI Digitizers.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022
2021
IEEE Trans. Circuits Syst. II Express Briefs, 2021
Design of Low-Voltage Power Efficient Frequency Dividers in Folded MOS Current Mode Logic.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021
IEEE Open J. Circuits Syst., 2021
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021
2020
A Novel 0.5 V MCML D-Flip-Flop Topology Exploiting Forward Body Bias Threshold Lowering.
IEEE Trans. Circuits Syst. II Express Briefs, 2020
Microelectron. J., 2020
An improved reversed miller compensation technique for three-stage CMOS OTAs with double pole-zero cancellation and almost single-pole frequency response.
Int. J. Circuit Theory Appl., 2020
Low-power class-AB 4th-order low-pass filter based on current conveyors with dynamic mismatch compensation of biasing errors.
Int. J. Circuit Theory Appl., 2020
0.6-V CMOS cascode OTA with complementary gate-driven gain-boosting and forward body bias.
Int. J. Circuit Theory Appl., 2020
Proceedings of the 2020 IEEE International Instrumentation and Measurement Technology Conference, 2020
2019
High-gain, high-CMRR class AB operational transconductance amplifier based on the flipped voltage follower.
Int. J. Circuit Theory Appl., 2019
Area-Efficient Low-Power Bandpass Gm-C Filter for Epileptic Seizure Detection in 130nm CMOS.
Proceedings of the 26th IEEE International Conference on Electronics, Circuits and Systems, 2019
Proceedings of the 26th IEEE International Conference on Electronics, Circuits and Systems, 2019
2018
Secure Double Rate Registers as an RTL Countermeasure Against Power Analysis Attacks.
IEEE Trans. Very Large Scale Integr. Syst., 2018
New Models for the Calibration of Four-Channel Time-Interleaved ADCs Using Filter Banks.
IEEE Trans. Circuits Syst. II Express Briefs, 2018
IEEE Trans. Circuits Syst. II Express Briefs, 2018
TEL Logic Style as a Countermeasure Against Side-Channel Attacks: Secure Cells Library in 65nm CMOS and Experimental Results.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018
Proceedings of the 14th Conference on Ph.D. Research in Microelectronics and Electronics, 2018
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
Proceedings of the 25th IEEE International Conference on Electronics, Circuits and Systems, 2018
2017
IEEE Trans. Very Large Scale Integr. Syst., 2017
Univariate Power Analysis Attacks Exploiting Static Dissipation of Nanometer CMOS VLSI Circuits for Cryptographic Applications.
IEEE Trans. Emerg. Top. Comput., 2017
Calibration of Time-Interleaved ADCs via Hermitianity-Preserving Taylor Approximations.
IEEE Trans. Circuits Syst. II Express Briefs, 2017
Faster, Stabler, and Simpler - A Recursive-Least-Squares Algorithm Exploiting the Frisch-Waugh-Lovell Theorem.
IEEE Trans. Circuits Syst. II Express Briefs, 2017
0.9-V Class-AB Miller OTA in 0.35-µm CMOS With Threshold-Lowered Non-Tailed Differential Pair.
IEEE Trans. Circuits Syst. I Regul. Pap., 2017
A Novel Framework to Estimate the Path Delay Variability On the Back of an Envelope via the Fan-Out-of-4 Metric.
IEEE Trans. Circuits Syst. I Regul. Pap., 2017
Template attacks exploiting static power and application to CMOS lightweight crypto-hardware.
Int. J. Circuit Theory Appl., 2017
Design-oriented models for quick estimation of path delay variability via the fan-out-of-4 metric.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017
Proceedings of the IEEE International Instrumentation and Measurement Technology Conference, 2017
Perfect reconstruction filters for 4-channels time-interleaved ADC affected by mismatches.
Proceedings of the 2017 European Conference on Circuit Theory and Design, 2017
The recursive batch least squares filter: An efficient RLS filter for floating-point hardware.
Proceedings of the 2017 European Conference on Circuit Theory and Design, 2017
On the use of voltage conveyors for the synthesis of biquad filters and arbitrary networks.
Proceedings of the 2017 European Conference on Circuit Theory and Design, 2017
Proceedings of the 2017 European Conference on Circuit Theory and Design, 2017
Proceedings of the 2017 European Conference on Circuit Theory and Design, 2017
Proceedings of the 2017 European Conference on Circuit Theory and Design, 2017
Proceedings of the 2017 European Conference on Circuit Theory and Design, 2017
Proceedings of the 2017 European Conference on Circuit Theory and Design, 2017
Multivariate Analysis Exploiting Static Power on Nanoscale CMOS Circuits for Cryptographic Applications.
Proceedings of the Progress in Cryptology - AFRICACRYPT 2017, 2017
2016
Comparative performance analysis and complementary triode based CMFB circuits for fully differential class AB symmetrical OTAs with low power consumption.
Int. J. Circuit Theory Appl., 2016
A shared memory, parameterized and configurable in FPGA, for use in multiprocessor systems.
Proceedings of the 2016 MIXDES, 2016
Proceedings of the 2016 MIXDES, 2016
Proceedings of the 2016 MIXDES, 2016
Proceedings of the 2016 MIXDES, 2016
On-chip analog current equalizer as a countermeasure against side-channel attacks in CMOS nanometer technology.
Proceedings of the 2016 MIXDES, 2016
Implementation of the PRESENT-80 block cipher and analysis of its vulnerability to Side Channel Attacks Exploiting Static Power.
Proceedings of the 2016 MIXDES, 2016
2015
IEEE Trans. Circuits Syst. II Express Briefs, 2015
Design and validation through a frequency-based metric of a new countermeasure to protect nanometer ICs from side-channel attacks.
J. Cryptogr. Eng., 2015
High-tuning-range CMOS band-pass IF filter based on a low-<i>Q</i> cascaded biquad optimization technique.
Int. J. Circuit Theory Appl., 2015
2014
88-µ A 1-MHz Stray-Insensitive CMOS Current-Mode Interface IC for Differential Capacitive Sensors.
IEEE Trans. Circuits Syst. I Regul. Pap., 2014
Effectiveness of Leakage Power Analysis Attacks on DPA-Resistant Logic Styles Under Process Variations.
IEEE Trans. Circuits Syst. I Regul. Pap., 2014
Microelectron. J., 2014
Architecture and modeling of a novel optical beamforming network suitable for microwave photonics implementation.
Proceedings of the 21st International Conference Mixed Design of Integrated Circuits and Systems, 2014
Proceedings of the 21st International Conference Mixed Design of Integrated Circuits and Systems, 2014
Proceedings of the 21st International Conference Mixed Design of Integrated Circuits and Systems, 2014
Design of broad-band power amplifiers by means of an impedance transforming lossy equalizer.
Proceedings of the 21st International Conference Mixed Design of Integrated Circuits and Systems, 2014
Leakage Power Analysis attacks against a bit slice implementation of the Serpent block cipher.
Proceedings of the 21st International Conference Mixed Design of Integrated Circuits and Systems, 2014
Proceedings of the IEEE International Conference on Distributed Computing in Sensor Systems, 2014
2013
IEEE Trans. Circuits Syst. II Express Briefs, 2013
Adaptive frequency compensation for maximum and constant bandwidth feedback amplifiers.
Int. J. Circuit Theory Appl., 2013
Security Evaluation and Optimization of the Delay-based Dual-rail Pre-charge Logic in Presence of Early Evaluation of Data.
Proceedings of the SECRYPT 2013, 2013
Proceedings of the 20th International Conference Mixed Design of Integrated Circuits and Systems, 2013
A flip-flop implementation for the DPA-resistant Delay-based Dual-rail Pre-charge Logic family.
Proceedings of the 20th International Conference Mixed Design of Integrated Circuits and Systems, 2013
Proceedings of the 21st European Conference on Circuit Theory and Design, 2013
2012
IEEE Trans. Very Large Scale Integr. Syst., 2012
Efficient Digital Background Calibration of Time-Interleaved Pipeline Analog-to-Digital Converters.
IEEE Trans. Circuits Syst. I Regul. Pap., 2012
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012
Constant and maximum bandwidth feedback amplifier with adaptive frequency compensation.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012
2011
IEEE Trans. Very Large Scale Integr. Syst., 2011
IEEE Trans. Circuits Syst. I Regul. Pap., 2011
IEEE Trans. Circuits Syst. I Regul. Pap., 2011
Leakage Power Analysis attacks: Effectiveness on DPA resistant logic styles under process variations.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011
Proceedings of the 20th European Conference on Circuit Theory and Design, 2011
Proceedings of the 20th European Conference on Circuit Theory and Design, 2011
Proceedings of the 20th European Conference on Circuit Theory and Design, 2011
Proceedings of the 20th European Conference on Circuit Theory and Design, 2011
Proceedings of the 20th European Conference on Circuit Theory and Design, 2011
2010
IEEE Trans. Circuits Syst. I Regul. Pap., 2010
Leakage Power Analysis Attacks: A Novel Class of Attacks to Nanometer Cryptographic Circuits.
IEEE Trans. Circuits Syst. I Regul. Pap., 2010
Proceedings of the Information and Communications Security - 12th International Conference, 2010
2009
Analysis and Implementation of a Minimum-Supply Body-Biased CMOS Differential Amplifier Cell.
IEEE Trans. Very Large Scale Integr. Syst., 2009
IEEE Trans. Circuits Syst. II Express Briefs, 2009
A novel low-voltage low-power fully differential voltage and current gained CCII for floating impedance simulations.
Microelectron. J., 2009
Int. J. Circuit Theory Appl., 2009
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009
Proceedings of the 16th IEEE International Conference on Electronics, 2009
Proceedings of the 16th IEEE International Conference on Electronics, 2009
2008
IEEE Trans. Instrum. Meas., 2008
High-Level Side-Channel Attack Modeling and Simulation for Security-Critical Systems on Chips.
IEEE Trans. Dependable Secur. Comput., 2008
IET Circuits Devices Syst., 2008
EURASIP J. Adv. Signal Process., 2008
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2008
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008
Low voltage, low power, compact, high accuracy, high precision PTAT temperature sensor for deep sub-micron CMOS systems.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008
Dual op amp, LDO regulator with power supply gain suppression for CMOS smart sensors and microsystems.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008
A new dynamic differential logic style as a countermeasure to power analysis attacks.
Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, 2008
2007
A Dynamic and Differential CMOS Lookup Table with Data-Independent Power Consumption for Cryptographic Applications on Chip Cards.
IEEE Trans. Dependable Secur. Comput., 2007
IEEE Trans. Circuits Syst. II Express Briefs, 2007
The Universal Circuit Simulator: A Mixed-Signal Approach to n-Port Network and Impedance Synthesis.
IEEE Trans. Circuits Syst. I Regul. Pap., 2007
IEEE Trans. Circuits Syst. I Regul. Pap., 2007
IEEE Trans. Circuits Syst. II Express Briefs, 2007
IET Inf. Secur., 2007
A Statistical Model of Logic Gates for Monte Carlo Simulation Including On-Chip Variations.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2007
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007
Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007
Proceedings of the 18th European Conference on Circuit Theory and Design, 2007
Proceedings of the 18th European Conference on Circuit Theory and Design, 2007
Proceedings of the 18th European Conference on Circuit Theory and Design, 2007
Proceedings of the 18th European Conference on Circuit Theory and Design, 2007
Proceedings of the 18th European Conference on Circuit Theory and Design, 2007
A Sample-and-Hold Circuit with Very Low Gain Error for Time Interleaving Applications.
Proceedings of the 18th European Conference on Circuit Theory and Design, 2007
Proceedings of the 18th European Conference on Circuit Theory and Design, 2007
2006
IEEE Trans. Circuits Syst. II Express Briefs, 2006
Inverting closed-loop amplifier architecture with reduced gain error and high input impedance.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
Validation of a statistical non-linear model of GaAs HEMT MMIC's by hypothesis testing and principal components analysis.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
Proceedings of the Cryptographic Hardware and Embedded Systems, 2006
2005
A novel yield optimization technique for digital CMOS circuits design by means of process parameters run-time estimation and body bias active control.
IEEE Trans. Very Large Scale Integr. Syst., 2005
A 10-Gb/s CMU/CDR chip-set in SiGe BiCMOS commercial technology with multistandard capability.
IEEE Trans. Very Large Scale Integr. Syst., 2005
Design and Test of a Novel Programmable Clock Generator Semi-Custom Core for Energy-Efficient Systems-on-Chips.
J. Low Power Electron., 2005
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
A countermeasure against differential power analysis based on random delay insertion.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
Proceedings of the 2005 European Conference on Circuit Theory and Design, 2005
Proceedings of the 2005 European Conference on Circuit Theory and Design, 2005
2004
Yield Optimization by Means of Process Parameters Estimation: Comparison Between ABB and ASV Techniques.
Proceedings of the Integrated Circuit and System Design, 2004
A Power Consumption Randomization Countermeasure for DPA-Resistant Cryptographic Processors.
Proceedings of the Integrated Circuit and System Design, 2004
A high-speed low-voltage phase detector for clock recovery from NRZ data.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004
Robust three-state PFD architecture with enhanced frequency acquisition capabilities.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004
2003
A High-Speed Oscillator-Based Truly Random Number Source for Cryptographic Applications on a Smart Card IC.
IEEE Trans. Computers, 2003
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003
Proceedings of the 2003 10th IEEE International Conference on Electronics, 2003
Proceedings of the 2003 10th IEEE International Conference on Electronics, 2003
2002
Proceedings of the 2002 9th IEEE International Conference on Electronics, 2002
Proceedings of the 2002 9th IEEE International Conference on Electronics, 2002
Proceedings of the 2002 9th IEEE International Conference on Electronics, 2002
2001
An all-digital clock generator firm-core based on differential fine-tuned delay for reusable microprocessor cores.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001
2000
Proceedings of the 2000 International Symposium on Low Power Electronics and Design, 2000
1999
A Low-Power Microcontroller with on-Chip Self-Tuning Digital Clock-Generator for Variable-Load Applications.
Proceedings of the IEEE International Conference On Computer Design, 1999
1998
A monolithic 2.5-Gb/s clock and data recovery circuit based on Silicon bipolar technology.
Proceedings of the Broadband European Networks and Multimedia Services, 1998