Giuseppe Scotti
Orcid: 0000-0002-5650-8212
According to our database1,
Giuseppe Scotti
authored at least 138 papers
between 2002 and 2024.
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Bibliography
2024
Rail to Rail ICMR and High Performance ULV Standard-Cell-Based Comparator for Biomedical and IoT Applications.
IEEE Access, 2024
A Novel High Performance Standard-Cell Based ULV OTA Exploiting an Improved Basic Amplifier.
IEEE Access, 2024
2023
High-Accuracy Low-Cost Generalized Complex Pruned Volterra Models for Nonlinear Calibration.
IEEE Trans. Circuits Syst. I Regul. Pap., September, 2023
A Novel FPGA Implementation of the NAND-PUF with Minimal Resource Usage and High Reliability.
Cryptogr., June, 2023
A body-driven rail-to-rail 0.3 V operational transconductance amplifier exploiting current gain stages.
Int. J. Circuit Theory Appl., May, 2023
IEEE Trans. Circuits Syst. I Regul. Pap., February, 2023
Exploiting the DD-Cell as an Ultra-Compact Entropy Source for an FPGA-Based Re-Configurable PUF-TRNG Architecture.
IEEE Access, 2023
A 0.3V Rail-to-Rail Three-Stage OTA With High DC Gain and Improved Robustness to PVT Variations.
IEEE Access, 2023
Proceedings of the 19th International Conference on Synthesis, 2023
Proceedings of the Applications in Electronics Pervading Industry, Environment and Society, 2023
2022
Enabling ULV Fully Synthesizable Analog Circuits: The BA Cell, a Standard-Cell-Based Building Block for Analog Design.
IEEE Trans. Circuits Syst. II Express Briefs, 2022
IEEE Trans. Circuits Syst. II Express Briefs, 2022
A Novel Ultra-Compact FPGA-Compatible TRNG Architecture Exploiting Latched Ring Oscillators.
IEEE Trans. Circuits Syst. II Express Briefs, 2022
High-Throughput FPGA-Compatible TRNG Architecture Exploiting Multistimuli Metastable Cells.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022
A SiGe HBT 6th-Order 10 GHz Inductor-Less Anti-Aliasing Low-Pass Filter for High-Speed ATI Digitizers.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022
A Novel Differential to Single-Ended Converter for Ultra-Low-Voltage Inverter-Based OTAs.
IEEE Access, 2022
A Novel Clock Gating Approach for the Design of Low-Power Linear Feedback Shift Registers.
IEEE Access, 2022
A Biasing Approach to Design Ultra-Low-Power Standard-Cell-Based Analog Building Blocks for Nanometer SoCs.
IEEE Access, 2022
Proceedings of the 17th Conference on Ph.D Research in Microelectronics and Electronics, 2022
Proceedings of the 17th Conference on Ph.D Research in Microelectronics and Electronics, 2022
Proceedings of the 17th Conference on Ph.D Research in Microelectronics and Electronics, 2022
2021
A Very-Low-Voltage Frequency Divider in Folded MOS Current Mode Logic With Complementary n- and p-type Flip-Flops.
IEEE Trans. Very Large Scale Integr. Syst., 2021
Design of Low-Voltage Power Efficient Frequency Dividers in Folded MOS Current Mode Logic.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021
IEEE Open J. Circuits Syst., 2021
IEEE Micro, 2021
Cryptogr., 2021
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021
2020
A Novel 0.5 V MCML D-Flip-Flop Topology Exploiting Forward Body Bias Threshold Lowering.
IEEE Trans. Circuits Syst. II Express Briefs, 2020
IEEE Trans. Circuits Syst., 2020
SC-DDPL: A Novel Standard-Cell Based Approach for Counteracting Power Analysis Attacks in the Presence of Unbalanced Routing.
IEEE Trans. Circuits Syst. I Regul. Pap., 2020
Microelectron. J., 2020
An improved reversed miller compensation technique for three-stage CMOS OTAs with double pole-zero cancellation and almost single-pole frequency response.
Int. J. Circuit Theory Appl., 2020
0.6-V CMOS cascode OTA with complementary gate-driven gain-boosting and forward body bias.
Int. J. Circuit Theory Appl., 2020
CoRR, 2020
2019
Area-Efficient Low-Power Bandpass Gm-C Filter for Epileptic Seizure Detection in 130nm CMOS.
Proceedings of the 26th IEEE International Conference on Electronics, Circuits and Systems, 2019
2018
Secure Double Rate Registers as an RTL Countermeasure Against Power Analysis Attacks.
IEEE Trans. Very Large Scale Integr. Syst., 2018
TEL Logic Style as a Countermeasure Against Side-Channel Attacks: Secure Cells Library in 65nm CMOS and Experimental Results.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018
Proceedings of the 14th Conference on Ph.D. Research in Microelectronics and Electronics, 2018
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
Proceedings of the 25th IEEE International Conference on Electronics, Circuits and Systems, 2018
Proceedings of the IEEE International Conference on Bioinformatics and Biomedicine, 2018
2017
IEEE Trans. Very Large Scale Integr. Syst., 2017
Univariate Power Analysis Attacks Exploiting Static Dissipation of Nanometer CMOS VLSI Circuits for Cryptographic Applications.
IEEE Trans. Emerg. Top. Comput., 2017
0.9-V Class-AB Miller OTA in 0.35-µm CMOS With Threshold-Lowered Non-Tailed Differential Pair.
IEEE Trans. Circuits Syst. I Regul. Pap., 2017
A Novel Framework to Estimate the Path Delay Variability On the Back of an Envelope via the Fan-Out-of-4 Metric.
IEEE Trans. Circuits Syst. I Regul. Pap., 2017
A Decomposition of the Tikhonov Regularization Functional Oriented to Exploit Hybrid Multilevel Parallelism.
Int. J. Parallel Program., 2017
Template attacks exploiting static power and application to CMOS lightweight crypto-hardware.
Int. J. Circuit Theory Appl., 2017
Design-oriented models for quick estimation of path delay variability via the fan-out-of-4 metric.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017
Proceedings of the 2017 European Conference on Circuit Theory and Design, 2017
Multivariate Analysis Exploiting Static Power on Nanoscale CMOS Circuits for Cryptographic Applications.
Proceedings of the Progress in Cryptology - AFRICACRYPT 2017, 2017
2016
On-chip analog current equalizer as a countermeasure against side-channel attacks in CMOS nanometer technology.
Proceedings of the 2016 MIXDES, 2016
Implementation of the PRESENT-80 block cipher and analysis of its vulnerability to Side Channel Attacks Exploiting Static Power.
Proceedings of the 2016 MIXDES, 2016
2015
Design and validation through a frequency-based metric of a new countermeasure to protect nanometer ICs from side-channel attacks.
J. Cryptogr. Eng., 2015
High-tuning-range CMOS band-pass IF filter based on a low-<i>Q</i> cascaded biquad optimization technique.
Int. J. Circuit Theory Appl., 2015
Towards a parallel component in a GPU-CUDA environment: a case study with the L-BFGS Harwell routine.
Int. J. Comput. Math., 2015
2014
88-µ A 1-MHz Stray-Insensitive CMOS Current-Mode Interface IC for Differential Capacitive Sensors.
IEEE Trans. Circuits Syst. I Regul. Pap., 2014
Effectiveness of Leakage Power Analysis Attacks on DPA-Resistant Logic Styles Under Process Variations.
IEEE Trans. Circuits Syst. I Regul. Pap., 2014
Design of broad-band power amplifiers by means of an impedance transforming lossy equalizer.
Proceedings of the 21st International Conference Mixed Design of Integrated Circuits and Systems, 2014
Leakage Power Analysis attacks against a bit slice implementation of the Serpent block cipher.
Proceedings of the 21st International Conference Mixed Design of Integrated Circuits and Systems, 2014
Proceedings of the 2014 International Conference on Intelligent Networking and Collaborative Systems, 2014
2013
Adaptive frequency compensation for maximum and constant bandwidth feedback amplifiers.
Int. J. Circuit Theory Appl., 2013
Security Evaluation and Optimization of the Delay-based Dual-rail Pre-charge Logic in Presence of Early Evaluation of Data.
Proceedings of the SECRYPT 2013, 2013
A flip-flop implementation for the DPA-resistant Delay-based Dual-rail Pre-charge Logic family.
Proceedings of the 20th International Conference Mixed Design of Integrated Circuits and Systems, 2013
Proceedings of the 21st European Conference on Circuit Theory and Design, 2013
2012
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012
Constant and maximum bandwidth feedback amplifier with adaptive frequency compensation.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012
2011
IEEE Trans. Very Large Scale Integr. Syst., 2011
IEEE Trans. Circuits Syst. I Regul. Pap., 2011
IEEE Trans. Circuits Syst. I Regul. Pap., 2011
Leakage Power Analysis attacks: Effectiveness on DPA resistant logic styles under process variations.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011
Proceedings of the 20th European Conference on Circuit Theory and Design, 2011
Proceedings of the 20th European Conference on Circuit Theory and Design, 2011
2010
Leakage Power Analysis Attacks: A Novel Class of Attacks to Nanometer Cryptographic Circuits.
IEEE Trans. Circuits Syst. I Regul. Pap., 2010
A modified damped Richardson-Lucy algorithm to reduce isotropic background effects in spherical deconvolution.
NeuroImage, 2010
Proceedings of the Information and Communications Security - 12th International Conference, 2010
2009
Analysis and Implementation of a Minimum-Supply Body-Biased CMOS Differential Amplifier Cell.
IEEE Trans. Very Large Scale Integr. Syst., 2009
IEEE Trans. Circuits Syst. II Express Briefs, 2009
A novel low-voltage low-power fully differential voltage and current gained CCII for floating impedance simulations.
Microelectron. J., 2009
Int. J. Circuit Theory Appl., 2009
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009
Proceedings of the 16th IEEE International Conference on Electronics, 2009
Proceedings of the 16th IEEE International Conference on Electronics, 2009
2008
IEEE Trans. Medical Imaging, 2008
IEEE Trans. Instrum. Meas., 2008
The topographical distribution of tissue injury in benign MS: A 3T multiparametric MRI study.
NeuroImage, 2008
Motor and language DTI Fiber Tracking combined with intraoperative subcortical mapping for surgical removal of gliomas.
NeuroImage, 2008
IET Circuits Devices Syst., 2008
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2008
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008
Low voltage, low power, compact, high accuracy, high precision PTAT temperature sensor for deep sub-micron CMOS systems.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008
Dual op amp, LDO regulator with power supply gain suppression for CMOS smart sensors and microsystems.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008
A new dynamic differential logic style as a countermeasure to power analysis attacks.
Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, 2008
2007
IEEE Trans. Circuits Syst. II Express Briefs, 2007
The Universal Circuit Simulator: A Mixed-Signal Approach to n-Port Network and Impedance Synthesis.
IEEE Trans. Circuits Syst. I Regul. Pap., 2007
IEEE Trans. Circuits Syst. I Regul. Pap., 2007
IEEE Trans. Circuits Syst. II Express Briefs, 2007
A Model-Based Deconvolution Approach to Solve Fiber Crossing in Diffusion-Weighted MR Imaging.
IEEE Trans. Biomed. Eng., 2007
A Statistical Model of Logic Gates for Monte Carlo Simulation Including On-Chip Variations.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2007
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007
Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007
Proceedings of the 18th European Conference on Circuit Theory and Design, 2007
Proceedings of the 18th European Conference on Circuit Theory and Design, 2007
Proceedings of the 18th European Conference on Circuit Theory and Design, 2007
Proceedings of the 18th European Conference on Circuit Theory and Design, 2007
Proceedings of the 18th European Conference on Circuit Theory and Design, 2007
2006
IEEE Trans. Circuits Syst. II Express Briefs, 2006
Inverting closed-loop amplifier architecture with reduced gain error and high input impedance.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
Validation of a statistical non-linear model of GaAs HEMT MMIC's by hypothesis testing and principal components analysis.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
2005
A novel yield optimization technique for digital CMOS circuits design by means of process parameters run-time estimation and body bias active control.
IEEE Trans. Very Large Scale Integr. Syst., 2005
A 10-Gb/s CMU/CDR chip-set in SiGe BiCMOS commercial technology with multistandard capability.
IEEE Trans. Very Large Scale Integr. Syst., 2005
A whole brain MR spectroscopy study from patients with Alzheimer's disease and mild cognitive impairment.
NeuroImage, 2005
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
Proceedings of the 2005 European Conference on Circuit Theory and Design, 2005
Proceedings of the 2005 European Conference on Circuit Theory and Design, 2005
2004
Pyramidal tract lesions and movement-associated cortical recruitment in patients with MS.
NeuroImage, 2004
A functional MRI study of movement-associated cortical changes in patients with Devic's neuromyelitis optica.
NeuroImage, 2004
A functional MRI study of cortical activations associated with object manipulation in patients with MS.
NeuroImage, 2004
Yield Optimization by Means of Process Parameters Estimation: Comparison Between ABB and ASV Techniques.
Proceedings of the Integrated Circuit and System Design, 2004
A high-speed low-voltage phase detector for clock recovery from NRZ data.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004
2003
Functional cortical changes in patients with multiple sclerosis and nonspecific findings on conventional magnetic resonance imaging scans of the brain.
NeuroImage, 2003
Evidence for axonal pathology and adaptive cortical reorganization in patients at presentation with clinically isolated syndromes suggestive of multiple sclerosis.
NeuroImage, 2003
A functional magnetic resonance imaging study of patients with secondary progressive multiple sclerosis.
NeuroImage, 2003
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003
2002
Correlations between Structural CNS Damage and Functional MRI Changes in Primary Progressive MS.
NeuroImage, 2002
NeuroImage, 2002