Francesco Menichelli
Orcid: 0000-0002-8453-6536
According to our database1,
Francesco Menichelli
authored at least 44 papers
between 2004 and 2023.
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Bibliography
2023
A Universal Hardware Emulator for Verification IPs on FPGA: A Novel and Low-Cost Approach.
Proceedings of the Applications in Electronics Pervading Industry, Environment and Society, 2023
Proceedings of the Applications in Electronics Pervading Industry, Environment and Society, 2023
Single Event Transient Reliability Analysis on a Fault-Tolerant RISC-V Microprocessor Design.
Proceedings of the Applications in Electronics Pervading Industry, Environment and Society, 2023
2022
Design and Evaluation of Buffered Triple Modular Redundancy in Interleaved-Multi-Threading Processors.
IEEE Access, 2022
Analysis of a Fault Tolerant Edge-Computing Microarchitecture Exploiting Vector Acceleration.
Proceedings of the 17th Conference on Ph.D Research in Microelectronics and Electronics, 2022
Proceedings of the Applications in Electronics Pervading Industry, Environment and Society, 2022
Proceedings of the Applications in Electronics Pervading Industry, Environment and Society, 2022
2021
IEEE Micro, 2021
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021
A Fault Tolerant soft-core obtained from an Interleaved-Multi- Threading RISC- V microprocessor design.
Proceedings of the 36th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2021
2020
CoRR, 2020
Fault resilience analysis of a RISC-V microprocessor design through a dedicated UVM environment.
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2020
2019
J. Low Power Electron., 2019
Proceedings of the 15th Conference on Ph.D. Research in Microelectronics and Electronics, 2019
Proceedings of the Applications in Electronics Pervading Industry, Environment and Society, 2019
Efficient Mathematical Accelerator Design Coupled with an Interleaved Multi-threading RISC-V Microprocessor.
Proceedings of the Applications in Electronics Pervading Industry, Environment and Society, 2019
A RISC-V Fault-Tolerant Microcontroller Core Architecture Based on a Hardware Thread Full/Partial Protection and a Thread-Controlled Watch-Dog Timer.
Proceedings of the Applications in Electronics Pervading Industry, Environment and Society, 2019
2018
Proceedings of the High Performance Computing, 2018
Proceedings of the 2018 New Generation of CAS, 2018
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
Proceedings of the Applications in Electronics Pervading Industry, Environment and Society, 2018
Proceedings of the Applications in Electronics Pervading Industry, Environment and Society, 2018
2017
Investigation on the Optimal Pipeline Organization in RISC-V Multi-threaded Soft Processor Cores.
Proceedings of the New Generation of CAS, 2017
The Microarchitecture of a Multi-threaded RISC-V Compliant Processing Core Family for IoT End-Nodes.
Proceedings of the Applications in Electronics Pervading Industry, Environment and Society, 2017
2016
Proceedings of the Applications in Electronics Pervading Industry, Environment and Society, 2016
2015
Narrowband Delay Tolerant Protocols for WSN Applications: Characterization and Selection Guide.
Proceedings of the Applications in Electronics Pervading Industry, Environment and Society, 2015
2014
A Regulation-Based Security Evaluation Method for Data Link in Wireless Sensor Network.
J. Comput. Networks Commun., 2014
A Platform-Based Emulator for Mass-Storage Flash Cards Evaluation in Embedded Systems.
Proceedings of the Applications in Electronics Pervading Industry, Environment and Society, 2014
Proceedings of the Applications in Electronics Pervading Industry, Environment and Society, 2014
2013
Wireless and Ad Hoc Sensor Networks: An Industrial Example Using Delay Tolerant, Low Power Protocols for Security-Critical Applications.
Proceedings of the Applications in Electronics Pervading Industry, Environment and Society, 2013
2012
Delay-Tolerant, Low-Power Protocols for Large Security-Critical Wireless Sensor Networks.
J. Comput. Networks Commun., 2012
Scalable virtual prototyping of distributed embedded control in a modern elevator system.
Proceedings of the 7th IEEE International Symposium on Industrial Embedded Systems, 2012
2011
Performance evaluation of Jpeg2000 implementation on VLIW cores, SIMD cores and multi-cores.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011
2010
TikTak: A Scalable Simulator of Wireless Sensor Networks Including Hardware/Software Interaction.
Wirel. Sens. Netw., 2010
2009
Static Minimization of Total Energy Consumption in Memory Subsystem for Scratchpad-Based Systems-on-Chips.
IEEE Trans. Very Large Scale Integr. Syst., 2009
2008
High-Level Side-Channel Attack Modeling and Simulation for Security-Critical Systems on Chips.
IEEE Trans. Dependable Secur. Comput., 2008
2007
IET Inf. Secur., 2007
2006
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
2005
Tecniche di analisi e progetto di architetture di sistemi a microprocessore integrati su singolo chip caratterizzati da criticità nei consumi di potenza.
PhD thesis, 2005
J. VLSI Signal Process., 2005
Software optimization of the JPEG2000 algorithm on a VLIW CPU core for system-on-chip implementation.
Proceedings of the Third IASTED International Conference on Circuits, 2005
2004
A Class of Code Compression Schemes for Reducing Power Consumption in Embedded Microprocessor Systems.
IEEE Trans. Computers, 2004
A Simulation-Based Power-Aware Architecture Exploration of a Multiprocessor System-on-Chip Design.
Proceedings of the 2004 Design, 2004
Proceedings of the 2004 International Conference on Compilers, 2004