Margarida F. Jacome

According to our database1, Margarida F. Jacome authored at least 53 papers between 1992 and 2009.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Links

On csauthors.net:

Bibliography

2009
Program slicing across the hardware-software boundary for embedded systems.
Int. J. Embed. Syst., 2009

Compiler Controlled Speculation for Power Aware ILP Extraction in Dataflow Architectures.
Proceedings of the High Performance Embedded Architectures and Compilers, 2009

Power Aware Embedded Computing.
Proceedings of the Embedded Systems Design and Verification, 2009

2007
Defect-Aware High-Level Synthesis Targeted at Reconfigurable Nanofabrics.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

Self-Imposed Temporal Redundancy: An Efficient Technique to Enhance the Reliability of Pipelined Functional Units.
Proceedings of the 19th Symposium on Computer Architecture and High Performance Computing (SBAC-PAD 2007), 2007

An RFID-Based Platform Supporting Context-Aware Computing in Complex Spaces.
Proceedings of the 8th International Conference on Mobile Data Management (MDM 2007), 2007

Global Optimization of Compositional Systems.
Proceedings of the Formal Methods in Computer-Aided Design, 7th International Conference, 2007

2006
RAS-NANO: a reliability-aware synthesis framework for reconfigurable nanofabrics.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006

2005
Power Aware Embedded Computing.
Proceedings of the Embedded Systems Handbook., 2005

Xtream-fit: an energy-delay efficient data memory subsystem for embedded media processing.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005

Predicated switching - optimizing speculation on EPIC machines.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005

Energy-delay efficient data memory subsystems: suitable for embedded media "processing".
IEEE Signal Process. Mag., 2005

A Reconfiguration-Based Defect-Tolerant Design Paradigm for Nanotechnologies.
IEEE Des. Test Comput., 2005

Scalable defect mapping and configuration of memory-based nanofabrics.
Proceedings of the Tenth IEEE International High-Level Design Validation and Test Workshop 2005, Napa Valley, CA, USA, November 30, 2005

High performance computing on fault-prone nanotechnologies: novel microarchitecture techniques exploiting reliability-delay trade-offs.
Proceedings of the 42nd Design Automation Conference, 2005

Power Aware Embedded Computing.
Proceedings of the Industrial Information Technology Handbook, 2005

2004
Defect tolerant probabilistic design paradigm for nanotechnologies.
Proceedings of the 41th Design Automation Conference, 2004

2003
Special issue on power-aware embedded computing.
ACM Trans. Embed. Comput. Syst., 2003

A Case Study of a System Level Approach to Exploration of Queuing Management Schemes for Input Queue Packet Switches.
Proceedings of the 11th Euromicro Workshop on Parallel, 2003

Embedded Architect: A Tool for Early Performance Evaluation of Embedded Software.
Proceedings of the 25th International Conference on Software Engineering, 2003

Compiler-Directed ILP Extraction for Clustered VLIW/EPIC Machines: Predication, Speculation and Modulo Scheduling.
Proceedings of the 2003 Design, 2003

Architecture-level performance evaluation of component-based embedded systems.
Proceedings of the 40th Design Automation Conference, 2003

Compiler-Directed ILP Extraction for Clustered VLIW/EPIC Machines.
Proceedings of the Embedded Software for SoC, 2003

2002
Cluster assignment for high-performance embedded VLIW processors.
ACM Trans. Design Autom. Electr. Syst., 2002

Application-specific clustered VLIW datapaths: early exploration on a parameterized design space.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002

RS-FDRA: A register-sensitive software pipelining algorithm for embedded VLIW processors.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002

An Effective Software Pipelining Algorithm for Clustered Embedded VLIW Processors.
Des. Autom. Embed. Syst., 2002

Scenario-based software characterization as a contingency to traditional program profiling.
Proceedings of the International Conference on Compilers, 2002

2001
A Survey of Digital Design Reuse.
IEEE Des. Test Comput., 2001

CALiBeR: A Software Pipelining Algorithm for Clustered Embedded VLIW Processors.
Proceedings of the 2001 IEEE/ACM International Conference on Computer-Aided Design, 2001

High-Quality Operation Binding for Clustered VLIW Datapaths.
Proceedings of the 38th Design Automation Conference, 2001

Clustered VLIW Architectures with Predicated Switching.
Proceedings of the 38th Design Automation Conference, 2001

2000
Design Challenges for New Application-Specific Processors.
IEEE Des. Test Comput., 2000

Assessing Probabilistic Timing Constraints on System Performance.
Des. Autom. Embed. Syst., 2000

A Tight Area Upper Bound for Slicing Floorplans.
Proceedings of the 13th International Conference on VLSI Design (VLSI Design 2000), 2000

The Common Hardware and Software Object Model: CHSOM.
Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 2000

FDRA: A Software-Pipelining Algorithm for Embedded VLIW Processors.
Proceedings of the 13th International Symposium on System Synthesis, 2000

Symbolic Binding for Clustered VLIW ASIPs.
Proceedings of the IEEE International Conference On Computer Design: VLSI In Computers & Processors, 2000

Exploring Performance Tradeoffs for Clustered VLIW ASIPs.
Proceedings of the 2000 IEEE/ACM International Conference on Computer-Aided Design, 2000

A new technique for estimating lower bounds on latency for high level synthesis.
Proceedings of the 10th ACM Great Lakes Symposium on VLSI 2000, 2000

Heuristic tradeoffs between latency and energy consumption in register assignment.
Proceedings of the Eighth International Workshop on Hardware/Software Codesign, 2000

1999
Lower bound on latency for VLIW ASIP datapaths.
Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design, 1999

The Design Space Layer: Supporting Early Design Space Exploration for Core-Based Designs.
Proceedings of the 1999 Design, 1999

Resource constrained dataflow retiming heuristics for VLIW ASIPs.
Proceedings of the Seventh International Workshop on Hardware/Software Codesign, 1999

1998
Software power estimation and optimization for high performance, 32-bit embedded processors.
Proceedings of the International Conference on Computer Design: VLSI in Computers and Processors, 1998

A Hardwar Operating System for Dynamic Reconfiguration of FPGAs.
Proceedings of the Field-Programmable Logic and Applications, 1998

A Methodology for Task Based Partitioning and Scheduling of Dynamically Reconfigurable Systems.
Proceedings of the 6th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM '98), 1998

Hierarchical Algorithms for Assessing Probabilistic Constraints on System Performance.
Proceedings of the 35th Conference on Design Automation, 1998

1997
NREC: Risk Assessment and Planning of Complex Designs.
IEEE Des. Test Comput., 1997

Algorithm and architecture-level design space exploration using hierarchical data flows.
Proceedings of the 1997 International Conference on Application-Specific Systems, 1997

1996
A formal basis for design process planning and management.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1996

1992
Design assistance for CAD frameworks.
Proceedings of the conference on European design automation, 1992

Design Process Management for CAD Frameworks.
Proceedings of the 29th Design Automation Conference, 1992


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