Marcello Lajolo

According to our database, Marcello Lajolo authored at least 25 papers between 1998 and 2008.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2008

Variation tolerant NoC design by means of self-calibrating links.

Simone Medardoni, Marcello Lajolo, Davide Bertozzi

Proceedings of the Design, Automation and Test in Europe, 2008

2007

In Memoriam: Margarida F. Jacome.

Gustavo de Veciana, Marcello Lajolo, Chen He, Enrico Macii, Sachin S. Sapatnekar

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

Hardware scheduling support in SMP architectures.

André C. Nácul, Francesco Regazzoni, Marcello Lajolo

Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

2006

Hardware/software partitioning of operating systems: a behavioral synthesis approach.

Sathish Chandra, Francesco Regazzoni, Marcello Lajolo

Proceedings of the 16th ACM Great Lakes Symposium on VLSI 2006, Philadelphia, PA, USA, April 30, 2006

C-based Design of a Flexible Wrapper for Tiled Networks On Chip.

Subhek Garg, Marcello Lajolo

Proceedings of the Forum on specification and Design Languages, 2006

2005

SOFTENIT: a methodology for boosting the software content of system-on-chip designs.

Abhishek Mitra, Marcello Lajolo, Kanishka Lahiri

Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, 2005

Automatic synthesis of the Hardware/Software Interface.

Francesco Regazzoni, André C. Nácul, Marcello Lajolo

Proceedings of the Forum on specification and Design Languages, 2005

Interface-Centric Abstraction Level for Rapid HW/SW Integration.

André C. Nácul, Marcello Lajolo, T. Givarjis

Proceedings of the Forum on specification and Design Languages, 2005

2003

A Case Study of a System Level Approach to Exploration of Queuing Management Schemes for Input Queue Packet Switches.

Chen He, Marcello Lajolo, Margarida F. Jacome

Proceedings of the 11th Euromicro Workshop on Parallel, 2003

2002

Cosimulation-based power estimation for system-on-chip design.

Marcello Lajolo, Anand Raghunathan, Sujit Dey, Luciano Lavagno

IEEE Trans. Very Large Scale Integr. Syst., 2002

On the support of minimum service rates for input queue switches.

Dirceu Cavendish, Marcello Lajolo, Hongbo Liu

Proceedings of the IEEE International Conference on Communications, 2002

On the evaluation of fairness for input queue switches.

Dirceu Cavendish, Marcello Lajolo, Hongbo Liu

Proceedings of the IEEE International Conference on Communications, 2002

2001

Bus guardians: an effective solution for online detection and correction of faults affecting system-on-chip buses.

Marcello Lajolo

IEEE Trans. Very Large Scale Integr. Syst., 2001

Early Evaluation Of Bus Interconnects Dependability For System-On-Chip Designs.

Marcello Lajolo, Matteo Sonza Reorda, Massimo Violante

Proceedings of the 14th International Conference on VLSI Design (VLSI Design 2001), 2001

2000

Early Power Estimation for System-on-Chip Designs.

Marcello Lajolo, Luciano Lavagno, Matteo Sonza Reorda, Massimo Violante

Proceedings of the Integrated Circuit Design, 2000

Compilation-based software performance estimation for system level design.

Mihai T. Lazarescu, Jwahar R. Bammi, Edwin A. Harcourt, Luciano Lavagno, Marcello Lajolo

Proceedings of the IEEE International High-Level Design Validation and Test Workshop 2000, 2000

Behavioral-level test vector generation for system-on-chip designs.

Marcello Lajolo, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante, Luciano Lavagno

Proceedings of the IEEE International High-Level Design Validation and Test Workshop 2000, 2000

System-level test bench generation in a co-design framework.

Marcello Lajolo, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante, Luciano Lavagno

Proceedings of the 5th European Test Workshop, 2000

Evaluating System Dependability in a Co-Design Framework.

Marcello Lajolo, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante, Luciano Lavagno

Proceedings of the 2000 Design, 2000

Efficient Power Co-Estimation Techniques for System-on-Chip Design.

Marcello Lajolo, Anand Raghunathan, Sujit Dey, Luciano Lavagno

Proceedings of the 2000 Design, 2000

Automatic test bench generation for simulation-based validation.

Marcello Lajolo, Luciano Lavagno, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante

Proceedings of the Eighth International Workshop on Hardware/Software Codesign, 2000

1999

A compilation-based software estimation scheme for hardware/software co-simulation.

Marcello Lajolo, Mihai T. Lazarescu, Alberto L. Sangiovanni-Vincentelli

Proceedings of the Seventh International Workshop on Hardware/Software Codesign, 1999

Fast Instruction Cache Simulation Strategies in a Hardware/Software Co-Design Environment.

Marcello Lajolo, Luciano Lavagno, Alberto L. Sangiovanni-Vincentelli

Proceedings of the 1999 Conference on Asia South Pacific Design Automation, 1999

1998

Software timing analysis using HW/SW cosimulation and instruction set simulator.

Jie Liu, Marcello Lajolo, Alberto L. Sangiovanni-Vincentelli

Proceedings of the Sixth International Workshop on Hardware/Software Codesign, 1998

A case study on modeling shared memory access effects during performance analysis of HW/SW systems.

Marcello Lajolo, Anand Raghunathan, Sujit Dey, Luciano Lavagno, Alberto L. Sangiovanni-Vincentelli

Proceedings of the Sixth International Workshop on Hardware/Software Codesign, 1998