Mário P. Véstias

According to our database, Mário P. Véstias authored at least 64 papers between 2002 and 2024.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2024

Designing Deep Learning Models on FPGA with Multiple Heterogeneous Engines.

Miguel Reis, Mário P. Véstias, Horácio C. Neto

ACM Trans. Reconfigurable Technol. Syst., March, 2024

Enhancing Urban Intersection Efficiency: Visible Light Communication and Learning-Based Control for Traffic Signal Optimization and Vehicle Management.

Manuel Augusto M. Vieira, Gonçalo Galvão, Manuela Vieira, Paula Louro, Mário P. Véstias, Pedro Vieira

Symmetry, February, 2024

LiDAR 3D Object Detection in FPGA with Low Bitwidth Quantization.

Henrique B. Brum, Mário P. Véstias, Horácio C. Neto

Proceedings of the Applied Reconfigurable Computing. Architectures, Tools, and Applications, 2024

2023

Efficient Design of Low Bitwidth Convolutional Neural Networks on FPGA with Optimized Dot Product Units.

Mário P. Véstias, Rui Policarpo Duarte, José T. de Sousa, Horácio C. Neto

ACM Trans. Reconfigurable Technol. Syst., March, 2023

Energy-Efficient and Real-Time Wearable for Wellbeing-Monitoring IoT System Based on SoC-FPGA.

Maria Inês Frutuoso, Horácio C. Neto, Mário P. Véstias, Rui Policarpo Duarte

Algorithms, March, 2023

Smart Embedded System for Skin Cancer Classification.

Pedro F. Durães, Mário P. Véstias

Future Internet, February, 2023

2022

Onboard Processing of Synthetic Aperture Radar Backprojection Algorithm in FPGA.

David Mota, Helena Cruz, Pedro R. Miranda, Rui Policarpo Duarte, José T. de Sousa, Horácio C. Neto, Mário P. Véstias

IEEE J. Sel. Top. Appl. Earth Obs. Remote. Sens., 2022

A Review of Synthetic-Aperture Radar Image Formation Algorithms and Implementations: A Computational Perspective.

Helena Cruz, Mário P. Véstias, José Monteiro, Horácio C. Neto, Rui Policarpo Duarte

Remote. Sens., 2022

2021

Efficient Design of Pruned Convolutional Neural Networks on FPGA.

Mário P. Véstias

J. Signal Process. Syst., 2021

Configurable Hardware Core for IoT Object Detection.

Pedro R. Miranda, Daniel Pestana, João D. Lopes, Rui Policarpo Duarte, Mário P. Véstias, Horácio C. Neto, José T. de Sousa

Future Internet, 2021

Decimal Multiplication in FPGA with a Novel Decimal Adder/Subtractor.

Mário P. Véstias, Horácio C. Neto

Algorithms, 2021

IOb-Cache: A High-Performance Configurable Open-Source Cache.

João V. Roque, João D. Lopes, Mário P. Véstias, José T. de Sousa

Algorithms, 2021

A Full Featured Configurable Accelerator for Object Detection With YOLO.

Daniel Pestana, Pedro R. Miranda, João D. Lopes, Rui Policarpo Duarte, Mário P. Véstias, Horácio C. Neto, José T. de Sousa

IEEE Access, 2021

2020

Hyperspectral Compressive Sensing With a System-On-Chip FPGA.

José M. P. Nascimento, Mário P. Véstias, Gabriel Martín

IEEE J. Sel. Top. Appl. Earth Obs. Remote. Sens., 2020

A fast and scalable architecture to run convolutional neural networks in low density FPGAs.

Mário P. Véstias, Rui Policarpo Duarte, José T. de Sousa, Horácio C. Neto

Microprocess. Microsystems, 2020

Moving Deep Learning to the Edge.

Mário P. Véstias, Rui Policarpo Duarte, José T. de Sousa, Horácio C. Neto

Algorithms, 2020

A Configurable Architecture for Running Hybrid Convolutional Neural Networks in Low-Density FPGAs.

Mário P. Véstias, Rui Policarpo Duarte, José T. de Sousa, Horácio C. Neto

IEEE Access, 2020

Implementing CNNs Using a Linear Array of Full Mesh CGRAs.

Valter Mário, João D. Lopes, Mário P. Véstias, José T. de Sousa

Proceedings of the Applied Reconfigurable Computing. Architectures, Tools, and Applications, 2020

Processing Systems for Deep Learning Inference on Edge Devices.

Mário P. Véstias

Proceedings of the Convergence of Artificial Intelligence and the Internet of Things, 2020

2019

A Survey of Convolutional Neural Networks on Edge with Reconfigurable Computing.

Mário P. Véstias

Algorithms, 2019

Low Energy Heterogeneous Computing with Multiple RISC-V and CGRA Cores.

Luís Fiolhais, Fernando M. Gonçalves, Rui Policarpo Duarte, Mário P. Véstias, José T. de Sousa

Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

Hybrid Dot-Product Calculation for Convolutional Neural Networks in FPGA.

Mário P. Véstias, Rui Policarpo Duarte, José T. de Sousa, Horácio C. Neto

Proceedings of the 29th International Conference on Field Programmable Logic and Applications, 2019

Faster Convolutional Neural Networks in Low Density FPGAs Using Block Pruning.

Tiago Peres, Ana Gonçalves, Mário P. Véstias

Proceedings of the Applied Reconfigurable Computing - 15th International Symposium, 2019

Exploring Data Size to Run Convolutional Neural Networks in Low Density FPGAs.

Ana Gonçalves, Tiago Peres, Mário P. Véstias

Proceedings of the Applied Reconfigurable Computing - 15th International Symposium, 2019

2018

Improving the area of fast parallel decimal multipliers.

Mário P. Véstias, Horácio C. Neto

Microprocess. Microsystems, 2018

Lite-CNN: A High-Performance Architecture to Execute CNNs in Low Density FPGAs.

Mário P. Véstias, Rui Policarpo Duarte, José T. de Sousa, Horácio C. Neto

Proceedings of the 28th International Conference on Field Programmable Logic and Applications, 2018

2017

Decimal addition on FPGA based on a mixed BCD/excess-6 representation.

Horácio C. Neto, Mário P. Véstias

Microprocess. Microsystems, 2017

Parallel dot-products for deep learning on FPGA.

Mário P. Véstias, Rui Policarpo Duarte, José T. de Sousa, Horácio C. Neto

Proceedings of the 27th International Conference on Field Programmable Logic and Applications, 2017

K-means clustering on CGRA.

João D. Lopes, José T. de Sousa, Horácio C. Neto, Mário P. Véstias

Proceedings of the 27th International Conference on Field Programmable Logic and Applications, 2017

2016

XtokaxtikoX: A stochastic computing-based autonomous cyber-physical system.

Rui Policarpo Duarte, Horácio C. Neto, Mário P. Véstias

Proceedings of the IEEE International Conference on Rebooting Computing, 2016

Multi-core for K-means clustering on FPGA.

Jose Canilho, Mário P. Véstias, Horácio C. Neto

Proceedings of the 26th International Conference on Field Programmable Logic and Applications, 2016

2015

Designing Hardware/Software Systems for Embedded High-Performance Computing.

Mário P. Véstias, Rui Policarpo Duarte, Horácio C. Neto

CoRR, 2015

FPGA-based architecture for hyperspectral unmixing.

José M. P. Nascimento, Mário P. Véstias, Gabriel Martín

Proceedings of the 2015 IEEE International Geoscience and Remote Sensing Symposium, 2015

Enhancing stochastic computations via process variation.

Rui Policarpo Duarte, Mário P. Véstias, Horácio C. Neto

Proceedings of the 25th International Conference on Field Programmable Logic and Applications, 2015

Using Dynamic Reconfiguration to Reduce the Area of a JPEG Decoder on FPGA.

Tiago Rodrigues, Mário P. Véstias

Proceedings of the 2015 Euromicro Conference on Digital System Design, 2015

Sparse Matrix Multiplication on a Reconfigurable Many-Core Architecture.

João Pinhão, Wilson José, Horácio C. Neto, Mário P. Véstias

Proceedings of the 2015 Euromicro Conference on Digital System Design, 2015

2014

A Many-Core Overlay for High-Performance Embedded Computing on FPGAs.

Mário P. Véstias, Horácio C. Neto

CoRR, 2014

Trends of CPU, GPU and FPGA for high-performance computing.

Mário P. Véstias, Horácio C. Neto

Proceedings of the 24th International Conference on Field Programmable Logic and Applications, 2014

Efficient implementation of a single-precision floating-point arithmetic unit on FPGA.

Wilson José, Ana Rita Silva, Horácio C. Neto, Mário P. Véstias

Proceedings of the 24th International Conference on Field Programmable Logic and Applications, 2014

2013

Very low resource table-based FPGA evaluation of elementary functions.

Horácio C. Neto, Mário P. Véstias

Proceedings of the 2012 International Conference on Reconfigurable Computing and FPGAs, 2013

Design of a multiband full-rate ultra-wideband receiver in FPGA.

Mário P. Véstias, Horácio C. Neto, Helena Sarmento

Proceedings of the 4th IEEE Latin American Symposium on Circuits and Systems, 2013

Design of a massively parallel computing architecture for dense matrix multiplication.

Wilson José, Ana Rita Silva, Mário P. Véstias, Horácio C. Neto

Proceedings of the 4th IEEE Latin American Symposium on Circuits and Systems, 2013

A reconfigurable computing architecture using magnetic tunneling junction memories.

Victor Silva, Jorge R. Fernandes, Mário P. Véstias, Horácio C. Neto

Proceedings of the 23rd International Conference on Field programmable Logic and Applications, 2013

Analysis of matrix multiplication on high density Virtex-7 FPGA.

Wilson José, Ana Rita Silva, Horácio C. Neto, Mário P. Véstias

Proceedings of the 23rd International Conference on Field programmable Logic and Applications, 2013

2012

A High-Performance Reconfigurable Computing architecture using a magnetic configuration memory.

Victor Silva, Jorge R. Fernandes, Mário P. Véstias, Horácio C. Neto

Proceedings of the 2012 International Conference on Reconfigurable Computing and FPGAs, 2012

Non-volatile memory circuits for FIMS and TAS writing techniques on magnetic tunnelling junctions.

Victor Silva, Mário P. Véstias, Horácio C. Neto, Jorge R. Fernandes

Proceedings of the 19th IEEE International Conference on Electronics, Circuits and Systems, 2012

Tradeoffs in the design of sliding block Viterbi decoders for MB-OFDM UWB systems.

Mário P. Véstias, Helena Sarmento

Proceedings of the IEEE Second International Conference on Consumer Electronics - Berlin, 2012

Design of an IEEE 802.15.3c baseband processor in FPGA.

Mário P. Véstias, Helena Sarmento

Proceedings of the IEEE Second International Conference on Consumer Electronics - Berlin, 2012

Design and test of a MIMO Receiver based on the Alamouti scheme in FPGA.

Mário P. Véstias

Proceedings of the IEEE Second International Conference on Consumer Electronics - Berlin, 2012

Sliding block Viterbi decoders in FPGA.

Mário P. Véstias, Horácio C. Neto, Helena Sarmento

Proceedings of the 22nd International Conference on Field Programmable Logic and Applications (FPL), 2012

Design of High-Speed Viterbi Decoders on Virtex-6 FPGAs.

Mário P. Véstias, Horácio C. Neto, Helena Sarmento

Proceedings of the 15th Euromicro Conference on Digital System Design, 2012

Parallel Decimal Multipliers and Squarers Using Karatsuba-Ofman's Algorithm.

Mário P. Véstias, Horácio C. Neto

Proceedings of the 15th Euromicro Conference on Digital System Design, 2012

2011

Revisiting the Newton-Raphson Iterative Method for Decimal Division.

Mário P. Véstias, Horácio C. Neto

Proceedings of the International Conference on Field Programmable Logic and Applications, 2011

2009

Run-Time Reconfigurable Array Using Magnetic RAM.

Victor Silva, Luís Bica Oliveira, Jorge R. Fernandes, Mário P. Véstias, Horácio C. Neto

Proceedings of the 12th Euromicro Conference on Digital System Design, 2009

Double-precision Gauss-Jordan Algorithm with Partial Pivoting on FPGAs.

Rui Policarpo Duarte, Horácio C. Neto, Mário P. Véstias

Proceedings of the 12th Euromicro Conference on Digital System Design, 2009

2008

Decimal multiplier on FPGA using embedded binary multipliers.

Horácio C. Neto, Mário P. Véstias

Proceedings of the FPL 2008, 2008

Multiplier-based double precision floating point divider according to the IEEE-754 standard.

Vítor Silva, Rui Policarpo Duarte, Mário P. Véstias, Horácio C. Neto

Proceedings of the Reconfigurable Computing: Architectures, 2008

2007

Router Design for Application Specific Networks-on-Chip on Reconfigurable Systems.

Mário P. Véstias, Horácio C. Neto

Proceedings of the FPL 2007, 2007

2006

Area and performance optimization of a generic network-on-chip architecture.

Mário P. Véstias, Horácio C. Neto

Proceedings of the 19th Annual Symposium on Integrated Circuits and Systems Design, 2006

A Generic Network-on-Chip Architecture for Reconfigurable Systems: Implementation and Evaluation.

Mário P. Véstias, Horácio C. Neto

Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), 2006

Co-synthesis of a configurable SoC platform based on a network on chip architecture.

Mário P. Véstias, Horácio C. Neto

Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006

Area/Performance Improvement of NoC Architectures.

Mário P. Véstias, Horácio C. Neto

Proceedings of the Reconfigurable Computing: Architectures and Applications, 2006

2003

DALI: A Methodology for the Co-Design of Dataflow Applications on Hardware/Software Architectures.

Mário P. Véstias, Horácio C. Neto

Proceedings of the 16th Annual Symposium on Integrated Circuits and Systems Design, 2003

2002

System-Level Co-Synthesis of Dataflow Dominated Applications on Reconfigurable Hardware/Software Architectures.

Mário P. Véstias, Horácio C. Neto

Proceedings of the 13th IEEE International Workshop on Rapid System Prototyping (RSP 2002), 2002