José T. de Sousa

According to our database, José T. de Sousa authored at least 41 papers between 1991 and 2023.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2023

Efficient Design of Low Bitwidth Convolutional Neural Networks on FPGA with Optimized Dot Product Units.

Mário P. Véstias, Rui Policarpo Duarte, José T. de Sousa, Horácio C. Neto

ACM Trans. Reconfigurable Technol. Syst., March, 2023

2022

Onboard Processing of Synthetic Aperture Radar Backprojection Algorithm in FPGA.

David Mota, Helena Cruz, Pedro R. Miranda, Rui Policarpo Duarte, José T. de Sousa, Horácio C. Neto, Mário P. Véstias

IEEE J. Sel. Top. Appl. Earth Obs. Remote. Sens., 2022

2021

Configurable Hardware Core for IoT Object Detection.

Pedro R. Miranda, Daniel Pestana, João D. Lopes, Rui Policarpo Duarte, Mário P. Véstias, Horácio C. Neto, José T. de Sousa

Future Internet, 2021

IOb-Cache: A High-Performance Configurable Open-Source Cache.

João V. Roque, João D. Lopes, Mário P. Véstias, José T. de Sousa

Algorithms, 2021

A Full Featured Configurable Accelerator for Object Detection With YOLO.

Daniel Pestana, Pedro R. Miranda, João D. Lopes, Rui Policarpo Duarte, Mário P. Véstias, Horácio C. Neto, José T. de Sousa

IEEE Access, 2021

2020

A fast and scalable architecture to run convolutional neural networks in low density FPGAs.

Mário P. Véstias, Rui Policarpo Duarte, José T. de Sousa, Horácio C. Neto

Microprocess. Microsystems, 2020

Moving Deep Learning to the Edge.

Mário P. Véstias, Rui Policarpo Duarte, José T. de Sousa, Horácio C. Neto

Algorithms, 2020

A Configurable Architecture for Running Hybrid Convolutional Neural Networks in Low-Density FPGAs.

Mário P. Véstias, Rui Policarpo Duarte, José T. de Sousa, Horácio C. Neto

IEEE Access, 2020

Implementing CNNs Using a Linear Array of Full Mesh CGRAs.

Valter Mário, João D. Lopes, Mário P. Véstias, José T. de Sousa

Proceedings of the Applied Reconfigurable Computing. Architectures, Tools, and Applications, 2020

2019

Low Energy Heterogeneous Computing with Multiple RISC-V and CGRA Cores.

Luís Fiolhais, Fernando M. Gonçalves, Rui Policarpo Duarte, Mário P. Véstias, José T. de Sousa

Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

Hybrid Dot-Product Calculation for Convolutional Neural Networks in FPGA.

Mário P. Véstias, Rui Policarpo Duarte, José T. de Sousa, Horácio C. Neto

Proceedings of the 29th International Conference on Field Programmable Logic and Applications, 2019

2018

Lite-CNN: A High-Performance Architecture to Execute CNNs in Low Density FPGAs.

Mário P. Véstias, Rui Policarpo Duarte, José T. de Sousa, Horácio C. Neto

Proceedings of the 28th International Conference on Field Programmable Logic and Applications, 2018

2017

Parallel dot-products for deep learning on FPGA.

Mário P. Véstias, Rui Policarpo Duarte, José T. de Sousa, Horácio C. Neto

Proceedings of the 27th International Conference on Field Programmable Logic and Applications, 2017

K-means clustering on CGRA.

João D. Lopes, José T. de Sousa, Horácio C. Neto, Mário P. Véstias

Proceedings of the 27th International Conference on Field Programmable Logic and Applications, 2017

2016

Versat, a Minimal Coarse-Grain Reconfigurable Array.

João D. Lopes, José T. de Sousa

Proceedings of the High Performance Computing for Computational Science - VECPAR 2016, 2016

2015

An ultra-low power low-IF GFSK demodulator for Bluetooth-LE applications.

Marco Silva Pereira, João Caldinhas Vaz, Carlos Azeredo Leme, José T. de Sousa, João Costa Freire

Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

2008

Decision heuristic for Davis Putnam, Loveland and Logemann algorithm satisfiability solving based on cube subtraction.

Romanelli Lodron Zuim, José T. de Sousa, Claudionor Coelho

IET Comput. Digit. Tech., 2008

2006

A Fast SAT Solver Strategy Based on Negated Clauses.

Romanelli Lodron Zuim, José T. de Sousa, Claudionor José Nunes Coelho Jr.

Proceedings of the IFIP VLSI-SoC 2006, 2006

A fast SAT solver algorithm best suited to reconfigurable hardware.

Romanelli Lodron Zuim, José T. de Sousa, Claudionor José Nunes Coelho Jr.

Proceedings of the 19th Annual Symposium on Integrated Circuits and Systems Design, 2006

2005

Heuristic-Based Backtracking Relaxation for Propositional Satisfiability.

Ateet Bhalla, Inês Lynce, José T. de Sousa, João Marques-Silva

J. Autom. Reason., 2005

A Low-Cost Scalable Pipelined Reconfigurable Architecture for Simulation of Digital Circuits.

Victor Gonçalves, José T. de Sousa, Fernando M. Gonçalves

Proceedings of the 2005 International Conference on Field Programmable Logic and Applications (FPL), 2005

2004

Guest Editors' Introduction: Field Programmable Logic and Applications.

Peter Y. K. Cheung, George A. Constantinides, José T. de Sousa

IEEE Trans. Computers, 2004

Solving SAT with a Context-Switching Virtual Clause Pipeline and an FPGA Embedded Processor.

Carlos J. Tavares, C. Bungardean, G. M. Matos, José T. de Sousa

Proceedings of the Field Programmable Logic and Application, 2004

2003

Heuristic Backtracking Algorithms for SAT.

Ateet Bhalla, Inês Lynce, José T. de Sousa, João Marques-Silva

Proceedings of the Fourth International Workshop on Microprocessor Test and Verification, 2003

Fault Simulation Using Partially Reconfigurable Hardware.

Abilio Parreira, João Paulo Teixeira, A. Pantelimon, Marcelino B. Santos, José T. de Sousa

Proceedings of the Field Programmable Logic and Application, 13th International Conference, 2003

Heuristic-Based Backtracking for Propositional Satisfiability.

Ateet Bhalla, Inês Lynce, José T. de Sousa, João Marques-Silva

Proceedings of the Progress in Artificial Intelligence, 2003

2002

DARP - A Digital Audio Reconfigurable Processor.

José T. de Sousa, Fernando M. Gonçalves, Nuno Barreiro, João Moura

Proceedings of the Field-Programmable Logic and Applications, 2002

On Implementing a Configware/Software SAT Solver.

N. A. Reis, José T. de Sousa

Proceedings of the 10th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2002), 2002

2001

A Configurable Hardware/Software Approach to SAT Solving.

José T. de Sousa, J. M. da Silva, Miron Abramovici

Proceedings of the 9th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, 2001

2000

A SAT Solver Using Reconfigurable Hardware and Virtual Logic.

Miron Abramovici, José T. de Sousa

J. Autom. Reason., 2000

Reducing the Complexity of Defect Level Modeling Using the Clustering Effect.

José T. de Sousa, Vishwani D. Agrawal

Proceedings of the 2000 Design, 2000

1999

On Defect-Level Estimation and the Clustering Effect.

José T. de Sousa

Proceedings of the VLSI: Systems on a Chip, 1999

A Virtual Logic Algorithm for Solving Satisfiability Problems Using Reconfigurable Hardware.

Miron Abramovici, José T. de Sousa

Proceedings of the 7th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM '99), 1999

A Massively-Parallel Easily-Scalable Satisfiability Solver Using Reconfigurable Hardware.

Miron Abramovici, José T. de Sousa, Daniel G. Saab

Proceedings of the 36th Conference on Design Automation, 1999

1997

Diagnosis of Boards for Realistic Interconnect Shorts.

José T. de Sousa, Peter Y. K. Cheung

J. Electron. Test., 1997

Improved diagnosis of realistic interconnect shorts.

José T. de Sousa, Peter Y. K. Cheung

Proceedings of the European Design and Test Conference, 1997

1996

Defect level evaluation in an IC design environment.

José T. de Sousa, Fernando M. Gonçalves, João Paulo Teixeira, Cristoforo Marzocca, Francesco Corsi, Thomas W. Williams

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1996

Realistic Fault Extraction for Boards.

José T. de Sousa, T. Shen, Peter Y. K. Cheung

Proceedings of the 1996 European Design and Test Conference, 1996

1994

Fault Modeling and Defect Level Projections in Digital ICs.

José T. de Sousa, Fernando M. Gonçalves, João Paulo Teixeira, Thomas W. Williams

Proceedings of the EDAC - The European Conference on Design Automation, ETC - European Test Conference, EUROASIC - The European Event in ASIC Design, Proceedings, February 28, 1994

1992

Physical DFT for High Coverage of Realistic Faults.

M. Saraiva, P. Casimiro, Marcelino B. Santos, José T. de Sousa, Fernando M. Gonçalves, Isabel C. Teixeira, João Paulo Teixeira

Proceedings of the Proceedings IEEE International Test Conference 1992, 1992

1991

IC Defects-Based Testability Analysis.

José T. de Sousa, Fernando M. Gonçalves, João Paulo Teixeira

Proceedings of the Proceedings IEEE International Test Conference 1991, 1991