Horácio C. Neto

According to our database, Horácio C. Neto authored at least 77 papers between 1992 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2024

Designing Deep Learning Models on FPGA with Multiple Heterogeneous Engines.

Miguel Reis, Mário P. Véstias, Horácio C. Neto

ACM Trans. Reconfigurable Technol. Syst., March, 2024

LiDAR 3D Object Detection in FPGA with Low Bitwidth Quantization.

Henrique B. Brum, Mário P. Véstias, Horácio C. Neto

Proceedings of the Applied Reconfigurable Computing. Architectures, Tools, and Applications, 2024

2023

Efficient Design of Low Bitwidth Convolutional Neural Networks on FPGA with Optimized Dot Product Units.

Mário P. Véstias, Rui Policarpo Duarte, José T. de Sousa, Horácio C. Neto

ACM Trans. Reconfigurable Technol. Syst., March, 2023

Energy-Efficient and Real-Time Wearable for Wellbeing-Monitoring IoT System Based on SoC-FPGA.

Maria Inês Frutuoso, Horácio C. Neto, Mário P. Véstias, Rui Policarpo Duarte

Algorithms, March, 2023

2022

Onboard Processing of Synthetic Aperture Radar Backprojection Algorithm in FPGA.

David Mota, Helena Cruz, Pedro R. Miranda, Rui Policarpo Duarte, José T. de Sousa, Horácio C. Neto, Mário P. Véstias

IEEE J. Sel. Top. Appl. Earth Obs. Remote. Sens., 2022

System on Chip (SoC) for Invisible Electrocardiography (ECG) Biometrics.

Francisco Melo, Horácio C. Neto, Hugo Plácido da Silva

Sensors, 2022

A Review of Synthetic-Aperture Radar Image Formation Algorithms and Implementations: A Computational Perspective.

Helena Cruz, Mário P. Véstias, José Monteiro, Horácio C. Neto, Rui Policarpo Duarte

Remote. Sens., 2022

2021

Configurable Hardware Core for IoT Object Detection.

Pedro R. Miranda, Daniel Pestana, João D. Lopes, Rui Policarpo Duarte, Mário P. Véstias, Horácio C. Neto, José T. de Sousa

Future Internet, 2021

Decimal Multiplication in FPGA with a Novel Decimal Adder/Subtractor.

Mário P. Véstias, Horácio C. Neto

Algorithms, 2021

A Full Featured Configurable Accelerator for Object Detection With YOLO.

Daniel Pestana, Pedro R. Miranda, João D. Lopes, Rui Policarpo Duarte, Mário P. Véstias, Horácio C. Neto, José T. de Sousa

IEEE Access, 2021

2020

A fast and scalable architecture to run convolutional neural networks in low density FPGAs.

Mário P. Véstias, Rui Policarpo Duarte, José T. de Sousa, Horácio C. Neto

Microprocess. Microsystems, 2020

Moving Deep Learning to the Edge.

Mário P. Véstias, Rui Policarpo Duarte, José T. de Sousa, Horácio C. Neto

Algorithms, 2020

A Configurable Architecture for Running Hybrid Convolutional Neural Networks in Low-Density FPGAs.

Mário P. Véstias, Rui Policarpo Duarte, José T. de Sousa, Horácio C. Neto

IEEE Access, 2020

Reconfigurable Accelerator for On-Board SAR Imaging Using the Backprojection Algorithm.

Rui Policarpo Duarte, Helena Cruz, Horácio C. Neto

Proceedings of the Applied Reconfigurable Computing. Architectures, Tools, and Applications, 2020

2019

Embedded Fault-Tolerant Accelerator Architecture for Synthetic-Aperture Radar Backprojection.

Helena Cruz, Rui Policarpo Duarte, Horácio C. Neto

J. Aerosp. Inf. Syst., November, 2019

kNN-STUFF: kNN STreaming Unit for Fpgas.

João Vieira, Rui Policarpo Duarte, Horácio C. Neto

IEEE Access, 2019

Hybrid Dot-Product Calculation for Convolutional Neural Networks in FPGA.

Mário P. Véstias, Rui Policarpo Duarte, José T. de Sousa, Horácio C. Neto

Proceedings of the 29th International Conference on Field Programmable Logic and Applications, 2019

Fault-Tolerant Architecture for On-board Dual-Core Synthetic-Aperture Radar Imaging.

Helena Cruz, Rui Policarpo Duarte, Horácio C. Neto

Proceedings of the Applied Reconfigurable Computing - 15th International Symposium, 2019

2018

Improving the area of fast parallel decimal multipliers.

Mário P. Véstias, Horácio C. Neto

Microprocess. Microsystems, 2018

FPGA-based OpenCL Accelerator for Discovering Temporal Patterns in Gene Expression Data Using Biclustering.

Rui Policarpo Duarte, Álvaro Simões, Rui Henriques, Horácio C. Neto

Proceedings of the 6th International Workshop on Parallelism in Bioinformatics, 2018

Lite-CNN: A High-Performance Architecture to Execute CNNs in Low Density FPGAs.

Mário P. Véstias, Rui Policarpo Duarte, José T. de Sousa, Horácio C. Neto

Proceedings of the 28th International Conference on Field Programmable Logic and Applications, 2018

An Efficient Exact Fused Dot Product Processor in FPGA.

Luís Fiolhais, Horácio C. Neto

Proceedings of the 28th International Conference on Field Programmable Logic and Applications, 2018

Stochastic Processors on FPGAs to Compute Sensor Data Towards Fault-Tolerant IoT Systems.

Rui Policarpo Duarte, Horácio C. Neto

Proceedings of the IEEE Conference on Dependable and Secure Computing, 2018

2017

Decimal addition on FPGA based on a mixed BCD/excess-6 representation.

Horácio C. Neto, Mário P. Véstias

Microprocess. Microsystems, 2017

Parallel dot-products for deep learning on FPGA.

Mário P. Véstias, Rui Policarpo Duarte, José T. de Sousa, Horácio C. Neto

Proceedings of the 27th International Conference on Field Programmable Logic and Applications, 2017

K-means clustering on CGRA.

João D. Lopes, José T. de Sousa, Horácio C. Neto, Mário P. Véstias

Proceedings of the 27th International Conference on Field Programmable Logic and Applications, 2017

2016

XtokaxtikoX: A stochastic computing-based autonomous cyber-physical system.

Rui Policarpo Duarte, Horácio C. Neto, Mário P. Véstias

Proceedings of the IEEE International Conference on Rebooting Computing, 2016

Multi-core for K-means clustering on FPGA.

Jose Canilho, Mário P. Véstias, Horácio C. Neto

Proceedings of the 26th International Conference on Field Programmable Logic and Applications, 2016

2015

Designing Hardware/Software Systems for Embedded High-Performance Computing.

Mário P. Véstias, Rui Policarpo Duarte, Horácio C. Neto

CoRR, 2015

FPGA redundancy recovery based on partial bitstreams for multiple partitions.

Victor M. Goncalves Martins, Joao Gabriel Reis, Horácio C. Neto, Eduardo Augusto Bezerra

Proceedings of the 16th Latin-American Test Symposium, 2015

A TMR Strategy with Enhanced Dependability Features Based on a Partial Reconfiguration Flow.

Victor M. Goncalves Martins, Paulo Ricardo Cechelero Villa, Horácio C. Neto, Eduardo Augusto Bezerra

Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015

Enhancing stochastic computations via process variation.

Rui Policarpo Duarte, Mário P. Véstias, Horácio C. Neto

Proceedings of the 25th International Conference on Field Programmable Logic and Applications, 2015

Designing Partial Bitstreams for Multiple Xilinx FPGA Partitions.

Victor M. Goncalves Martins, Joao Gabriel Reis, Horácio C. Neto, Eduardo Augusto Bezerra

Proceedings of the 23rd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2015

Sparse Matrix Multiplication on a Reconfigurable Many-Core Architecture.

João Pinhão, Wilson José, Horácio C. Neto, Mário P. Véstias

Proceedings of the 2015 Euromicro Conference on Digital System Design, 2015

2014

A Many-Core Overlay for High-Performance Embedded Computing on FPGAs.

Mário P. Véstias, Horácio C. Neto

CoRR, 2014

Trends of CPU, GPU and FPGA for high-performance computing.

Mário P. Véstias, Horácio C. Neto

Proceedings of the 24th International Conference on Field Programmable Logic and Applications, 2014

Efficient implementation of a single-precision floating-point arithmetic unit on FPGA.

Wilson José, Ana Rita Silva, Horácio C. Neto, Mário P. Véstias

Proceedings of the 24th International Conference on Field Programmable Logic and Applications, 2014

2013

Very low resource table-based FPGA evaluation of elementary functions.

Horácio C. Neto, Mário P. Véstias

Proceedings of the 2012 International Conference on Reconfigurable Computing and FPGAs, 2013

Design of a multiband full-rate ultra-wideband receiver in FPGA.

Mário P. Véstias, Horácio C. Neto, Helena Sarmento

Proceedings of the 4th IEEE Latin American Symposium on Circuits and Systems, 2013

Design of a massively parallel computing architecture for dense matrix multiplication.

Wilson José, Ana Rita Silva, Mário P. Véstias, Horácio C. Neto

Proceedings of the 4th IEEE Latin American Symposium on Circuits and Systems, 2013

A reconfigurable computing architecture using magnetic tunneling junction memories.

Victor Silva, Jorge R. Fernandes, Mário P. Véstias, Horácio C. Neto

Proceedings of the 23rd International Conference on Field programmable Logic and Applications, 2013

Analysis of matrix multiplication on high density Virtex-7 FPGA.

Wilson José, Ana Rita Silva, Horácio C. Neto, Mário P. Véstias

Proceedings of the 23rd International Conference on Field programmable Logic and Applications, 2013

2012

A High-Performance Reconfigurable Computing architecture using a magnetic configuration memory.

Victor Silva, Jorge R. Fernandes, Mário P. Véstias, Horácio C. Neto

Proceedings of the 2012 International Conference on Reconfigurable Computing and FPGAs, 2012

Non-volatile memory circuits for FIMS and TAS writing techniques on magnetic tunnelling junctions.

Victor Silva, Mário P. Véstias, Horácio C. Neto, Jorge R. Fernandes

Proceedings of the 19th IEEE International Conference on Electronics, Circuits and Systems, 2012

Sliding block Viterbi decoders in FPGA.

Mário P. Véstias, Horácio C. Neto, Helena Sarmento

Proceedings of the 22nd International Conference on Field Programmable Logic and Applications (FPL), 2012

Design of High-Speed Viterbi Decoders on Virtex-6 FPGAs.

Mário P. Véstias, Horácio C. Neto, Helena Sarmento

Proceedings of the 15th Euromicro Conference on Digital System Design, 2012

Parallel Decimal Multipliers and Squarers Using Karatsuba-Ofman's Algorithm.

Mário P. Véstias, Horácio C. Neto

Proceedings of the 15th Euromicro Conference on Digital System Design, 2012

2011

Revisiting the Newton-Raphson Iterative Method for Decimal Division.

Mário P. Véstias, Horácio C. Neto

Proceedings of the International Conference on Field Programmable Logic and Applications, 2011

2010

Reconfigurable Circuits Using Magnetic Tunneling Junction Memories.

Victor Silva, Jorge R. Fernandes, Horácio C. Neto

Proceedings of the Emerging Trends in Technological Innovation, 2010

2009

Unbalanced FIFO sorting for FPGA-based systems.

Rui Marcelino, Horácio C. Neto, João M. P. Cardoso

Proceedings of the 16th IEEE International Conference on Electronics, 2009

Run-Time Reconfigurable Array Using Magnetic RAM.

Victor Silva, Luís Bica Oliveira, Jorge R. Fernandes, Mário P. Véstias, Horácio C. Neto

Proceedings of the 12th Euromicro Conference on Digital System Design, 2009

Double-precision Gauss-Jordan Algorithm with Partial Pivoting on FPGAs.

Rui Policarpo Duarte, Horácio C. Neto, Mário P. Véstias

Proceedings of the 12th Euromicro Conference on Digital System Design, 2009

2008

Sorting Units for FPGA-Based Embedded Systems.

Rui Marcelino, Horácio C. Neto, João M. P. Cardoso

Proceedings of the Distributed Embedded Systems: Design, 2008

Decimal multiplier on FPGA using embedded binary multipliers.

Horácio C. Neto, Mário P. Véstias

Proceedings of the FPL 2008, 2008

Multiplier-based double precision floating point divider according to the IEEE-754 standard.

Vítor Silva, Rui Policarpo Duarte, Mário P. Véstias, Horácio C. Neto

Proceedings of the Reconfigurable Computing: Architectures, 2008

2007

Router Design for Application Specific Networks-on-Chip on Reconfigurable Systems.

Mário P. Véstias, Horácio C. Neto

Proceedings of the FPL 2007, 2007

2006

Area and performance optimization of a generic network-on-chip architecture.

Mário P. Véstias, Horácio C. Neto

Proceedings of the 19th Annual Symposium on Integrated Circuits and Systems Design, 2006

A Generic Network-on-Chip Architecture for Reconfigurable Systems: Implementation and Evaluation.

Mário P. Véstias, Horácio C. Neto

Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), 2006

On Reconfigurable Architectures for Efficient Matrix Inversion.

Goncalo M. de Matos, Horácio C. Neto

Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), 2006

Co-synthesis of a configurable SoC platform based on a network on chip architecture.

Mário P. Véstias, Horácio C. Neto

Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006

Area/Performance Improvement of NoC Architectures.

Mário P. Véstias, Horácio C. Neto

Proceedings of the Reconfigurable Computing: Architectures and Applications, 2006

2005

Data-Driven Regular Reconfigurable Arrays: Design Space Exploration and Mapping.

Ricardo S. Ferreira, João M. P. Cardoso, Andre Toledo, Horácio C. Neto

Proceedings of the Embedded Computer Systems: Architectures, 2005

An Efficient and Scalable Architecture for Neural Networks with Backpropagation Learning.

Pedro M. Domingos, Fernando M. Silva, Horácio C. Neto

Proceedings of the 2005 International Conference on Field Programmable Logic and Applications (FPL), 2005

2004

An Environment for Exploring Data-Driven Architectures.

Ricardo S. Ferreira, João M. P. Cardoso, Horácio C. Neto

Proceedings of the Field Programmable Logic and Application, 2004

2003

Compilation for FPGA-Based Reconfigurable Hardware.

João M. P. Cardoso, Horácio C. Neto

IEEE Des. Test Comput., 2003

DALI: A Methodology for the Co-Design of Dataflow Applications on Hardware/Software Architectures.

Mário P. Véstias, Horácio C. Neto

Proceedings of the 16th Annual Symposium on Integrated Circuits and Systems Design, 2003

2002

System-Level Co-Synthesis of Dataflow Dominated Applications on Reconfigurable Hardware/Software Architectures.

Mário P. Véstias, Horácio C. Neto

Proceedings of the 13th IEEE International Workshop on Rapid System Prototyping (RSP 2002), 2002

2001

An exact solution to the minimum size test pattern problem.

Paulo F. Flores, Horácio C. Neto, João P. Marques Silva

ACM Trans. Design Autom. Electr. Syst., 2001

Compilation Increasing the Scheduling Scope for Multi-memory-FPGA-Based Custom Computing Machines.

João M. P. Cardoso, Horácio C. Neto

Proceedings of the Field-Programmable Logic and Applications, 2001

1999

Assignment and Reordering of Incompletely Specified Pattern Sequences Targetting Minimum Power Dissipation.

Paulo F. Flores, José C. Costa, Horácio C. Neto, José Monteiro, João Marques-Silva

Proceedings of the 12th International Conference on VLSI Design (VLSI Design 1999), 1999

Test pattern generation for width compression in BIST.

Paulo F. Flores, Horácio C. Neto, Krishnendu Chakrabarty, João Marques-Silva

Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

An Enhanced Static-List Scheduling Algorithm for Temporal Partitioning onto RPUs.

João M. P. Cardoso, Horácio C. Neto

Proceedings of the VLSI: Systems on a Chip, 1999

On Applying Set Covering Models to Test Set Compaction.

Paulo F. Flores, Horácio C. Neto, João P. Marques Silva

Proceedings of the 9th Great Lakes Symposium on VLSI (GLS-VLSI '99), 1999

Macro-Based Hardware Compilation of Java(tm) Bytecodes into a Dynamic Reconfigurable Computing System.

João M. P. Cardoso, Horácio C. Neto

Proceedings of the 7th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM '99), 1999

1998

Towards an automatic path from Java^TM bytecodes to hardware through high-level synthesis.

João M. P. Cardoso, Horácio C. Neto

Proceedings of the 5th IEEE International Conference on Electronics, Circuits and Systems, 1998

1994

Bitwise Encoding of Finite State Machines.

José Monteiro, James H. Kukula, Srinivas Devadas, Horácio C. Neto

Proceedings of the Seventh International Conference on VLSI Design, 1994

1992

On exponential fitting for circuit simulation.

Luís Miguel Silveira, Jacob K. White, Horácio C. Neto, Luís M. Vidigal

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1992