Rui Policarpo Duarte
Orcid: 0000-0002-7060-4745
According to our database1,
Rui Policarpo Duarte
authored at least 35 papers
between 2008 and 2023.
Collaborative distances:
Collaborative distances:
Timeline
Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
On csauthors.net:
Bibliography
2023
Efficient Design of Low Bitwidth Convolutional Neural Networks on FPGA with Optimized Dot Product Units.
ACM Trans. Reconfigurable Technol. Syst., March, 2023
Energy-Efficient and Real-Time Wearable for Wellbeing-Monitoring IoT System Based on SoC-FPGA.
Algorithms, March, 2023
2022
IEEE J. Sel. Top. Appl. Earth Obs. Remote. Sens., 2022
A Review of Synthetic-Aperture Radar Image Formation Algorithms and Implementations: A Computational Perspective.
Remote. Sens., 2022
2021
IEEE Access, 2021
2020
A fast and scalable architecture to run convolutional neural networks in low density FPGAs.
Microprocess. Microsystems, 2020
A Configurable Architecture for Running Hybrid Convolutional Neural Networks in Low-Density FPGAs.
IEEE Access, 2020
Reconfigurable Accelerator for On-Board SAR Imaging Using the Backprojection Algorithm.
Proceedings of the Applied Reconfigurable Computing. Architectures, Tools, and Applications, 2020
2019
Embedded Fault-Tolerant Accelerator Architecture for Synthetic-Aperture Radar Backprojection.
J. Aerosp. Inf. Syst., November, 2019
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019
Proceedings of the 29th International Conference on Field Programmable Logic and Applications, 2019
Proceedings of the Applied Reconfigurable Computing - 15th International Symposium, 2019
2018
FPGA-based OpenCL Accelerator for Discovering Temporal Patterns in Gene Expression Data Using Biclustering.
Proceedings of the 6th International Workshop on Parallelism in Bioinformatics, 2018
Proceedings of the 28th International Conference on Field Programmable Logic and Applications, 2018
Stochastic Processors on FPGAs to Compute Sensor Data Towards Fault-Tolerant IoT Systems.
Proceedings of the IEEE Conference on Dependable and Secure Computing, 2018
2017
Transport Protocols for Large Bandwidth-Delay Product Networks - TCP Extensions and Alternative Transport Protocols.
CoRR, 2017
Proceedings of the 27th International Conference on Field Programmable Logic and Applications, 2017
2016
Proceedings of the International Conference on Embedded Computer Systems: Architectures, 2016
Proceedings of the Technological Innovation for Cyber-Physical Systems, 2016
Proceedings of the IEEE International Conference on Rebooting Computing, 2016
2015
ARC 2014 Over-Clocking KLT Designs on FPGAs under Process, Voltage, and Temperature Variation.
ACM Trans. Reconfigurable Technol. Syst., 2015
CoRR, 2015
Proceedings of the Machine Learning and Knowledge Discovery in Databases, 2015
Proceedings of the 25th International Conference on Field Programmable Logic and Applications, 2015
2014
Zero-latency datapath error correction framework for over-clocking DSP applications on FPGAs.
Proceedings of the 2014 International Conference on ReConFigurable Computing and FPGAs, 2014
Proceedings of the 2014 IEEE International Parallel & Distributed Processing Symposium Workshops, 2014
Pushing the performance boundary of linear projection designs through device specific optimisations (abstract only).
Proceedings of the 2014 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2014
A Unified Framework for Over-Clocking Linear Projections on FPGAs under PVT Variation.
Proceedings of the Reconfigurable Computing: Architectures, Tools, and Applications, 2014
2012
High-level linear projection circuit design optimization framework for FPGAs under over-clocking.
Proceedings of the 22nd International Conference on Field Programmable Logic and Applications (FPL), 2012
2009
Proceedings of the 12th Euromicro Conference on Digital System Design, 2009
2008
Multiplier-based double precision floating point divider according to the IEEE-754 standard.
Proceedings of the Reconfigurable Computing: Architectures, 2008