Fernando M. Gonçalves

According to our database, Fernando M. Gonçalves authored at least 31 papers between 1990 and 2019.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2019

Low Energy Heterogeneous Computing with Multiple RISC-V and CGRA Cores.

Luís Fiolhais, Fernando M. Gonçalves, Rui Policarpo Duarte, Mário P. Véstias, José T. de Sousa

Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

2016

Performance-driven instrumentation and mapping strategies using the LARA aspect-oriented programming approach.

João M. P. Cardoso, José Gabriel F. Coutinho, Tiago Carvalho, Pedro C. Diniz, Zlatko Petrov, Wayne Luk, Fernando M. Gonçalves

Softw. Pract. Exp., 2016

2014

High-Level Synthesis in the Delft Workbench Hardware/Software Co-design Tool-Chain.

Razvan Nane, Vlad Mihai Sima, Cuong Pham-Quoc, Fernando M. Gonçalves, Koen Bertels

Proceedings of the 12th IEEE International Conference on Embedded and Ubiquitous Computing, 2014

2012

Hardware/software specialization through aspects: The LARA approach.

João M. P. Cardoso, Tiago Carvalho, João Teixeira, Pedro C. Diniz, Fernando M. Gonçalves, Zlatko Petrov

Proceedings of the 2012 International Conference on Embedded Computer Systems: Architectures, 2012

2009

On-Detector Electronics of the Clear PEM Scanner.

Edgar F. M. Albuquerque, Vasco Bexiga, Ricardo Bugalho, Bruno Carriço, Cláudia S. Ferreira, Miguel Ferreira, Joaquim Godinho, Fernando M. Gonçalves, Carlos Leong, Pedro Lousã, Pedro Machado, Rui Moura, Pedro Neves, Catarina Ortigão, Fernando Piedade, João F. Pinheiro, P. Relvas, Angelo Rivetti, Pedro Miguel Rodrigues, José C. Silva, Manuel M. Silva, Isabel C. Teixeira, João Paulo Teixeira, Andreia Trindade, João Varela

Proceedings of the BIODEVICES 2009, 2009

2005

A Low-Cost Scalable Pipelined Reconfigurable Architecture for Simulation of Digital Circuits.

Victor Gonçalves, José T. de Sousa, Fernando M. Gonçalves

Proceedings of the 2005 International Conference on Field Programmable Logic and Applications (FPL), 2005

2003

Property Coverage for Quality Assessment of Fault Tolerant or Fail Safe Systems.

Fernando M. Gonçalves, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira

Proceedings of the 9th IEEE International On-Line Testing Symposium (IOLTS 2003), 2003

2002

RTL Design Validation, DFT and Test Pattern Generation for High Defects Coverage.

Marcelino B. Santos, Fernando M. Gonçalves, Isabel C. Teixeira, João Paulo Teixeira

J. Electron. Test., 2002

Design and Test of a Certifiable ASIC for a Safety-Critical Gas Burner Control System.

Fernando M. Gonçalves, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira

J. Electron. Test., 2002

DARP - A Digital Audio Reconfigurable Processor.

José T. de Sousa, Fernando M. Gonçalves, Nuno Barreiro, João Moura

Proceedings of the Field-Programmable Logic and Applications, 2002

Self-Checking and Fault Tolerance Quality Assessment Using Fault Sampling.

Fernando M. Gonçalves, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira

Proceedings of the 17th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2002), 2002

2001

RTL-Based Functional Test Generation for High Defects Coverage in Digital Systems.

Marcelino B. Santos, Fernando M. Gonçalves, Isabel C. Teixeira, João Paulo Teixeira

J. Electron. Test., 2001

Implicit functionality and multiple branch coverage (IFMB): a testability metric for RT-level.

Fernando M. Gonçalves, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira

Proceedings of the Proceedings IEEE International Test Conference 2001, Baltimore, MD, USA, 30 October, 2001

Design and Test of Certifiable ASICs for Safety-Critical Gas Burners Contro.

Fernando M. Gonçalves, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira

Proceedings of the 7th IEEE International On-Line Testing Workshop (IOLTW 2001), 2001

2000

RTL-based functional test generation for high defects coverage in digital SOCs.

Marcelino B. Santos, Fernando M. Gonçalves, Isabel C. Teixeira, João Paulo Teixeira

Proceedings of the 5th European Test Workshop, 2000

1999

Defect-Oriented Sampling of Non-Equally Probable Faults in VLSI Systems.

Fernando M. Gonçalves, João Paulo Teixeira

J. Electron. Test., 1999

Defect-Oriented Verilog Fault Simulation of SoC Macros using a Stratified Fault Sampling Technique.

Marcelino B. Santos, Fernando M. Gonçalves, Isabel C. Teixeira, João Paulo Teixeira

Proceedings of the 17th IEEE VLSI Test Symposium (VTS '99), 1999

Teaching Microelectronic-Based Integrated Systems Design and Test.

Fernando M. Gonçalves, João Paulo Teixeira

Proceedings of the IEEE International Conference on Microelectronic Systems Education, 1999

1998

Sampling Techniques of Non-Equally Probable Faults in VLSI System.

Fernando M. Gonçalves, João Paulo Teixeira

Proceedings of the 16th IEEE VLSI Test Symposium (VTS '98), 28 April, 1998

Defect-oriented test quality assessment using fault sampling and simulation.

Fernando M. Gonçalves, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira

Proceedings of the Proceedings IEEE International Test Conference 1998, 1998

Defect-oriented testing of analogue and mixed signal ICs.

Marcelino B. Santos, Fernando M. Gonçalves, Michael J. Ohletz, João Paulo Teixeira

Proceedings of the 5th IEEE International Conference on Electronics, Circuits and Systems, 1998

1997

Realistic Fault Extraction for High-Quality Design and Test of VLSI Systems.

Fernando M. Gonçalves, Isabel C. Teixeira, João Paulo Teixeira

Proceedings of the 1997 Workshop on Defect and Fault-Tolerance in VLSI Systems (DFT '97), 1997

1996

Defect level evaluation in an IC design environment.

José T. de Sousa, Fernando M. Gonçalves, João Paulo Teixeira, Cristoforo Marzocca, Francesco Corsi, Thomas W. Williams

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1996

Integrated Approach for Circuit and Fault Extraction of VLSI Circuits.

Fernando M. Gonçalves, Isabel C. Teixeira, João Paulo Teixeira

Proceedings of the 1996 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 1996

1994

Back Annotation of Physical Defects into Gate-Level, Realistic Faults in Digital ICs.

Mario Calha, Marcelino B. Santos, Fernando M. Gonçalves, Isabel C. Teixeira, João Paulo Teixeira

Proceedings of the Proceedings IEEE International Test Conference 1994, 1994

Fault Modeling and Defect Level Projections in Digital ICs.

José T. de Sousa, Fernando M. Gonçalves, João Paulo Teixeira, Thomas W. Williams

Proceedings of the EDAC - The European Conference on Design Automation, ETC - European Test Conference, EUROASIC - The European Event in ASIC Design, Proceedings, February 28, 1994

On the Analysis of Routing Cells and Adjacency Faults in CMOS Digital Circuits.

A. P. Casimiro, Fernando M. Gonçalves, João Paulo Teixeira, Marcelino B. Santos

Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems, 1994

1992

Physical DFT for High Coverage of Realistic Faults.

M. Saraiva, P. Casimiro, Marcelino B. Santos, José T. de Sousa, Fernando M. Gonçalves, Isabel C. Teixeira, João Paulo Teixeira

Proceedings of the Proceedings IEEE International Test Conference 1992, 1992

1991

A methodology for testability enhancement at layout level.

João Paulo Teixeira, Isabel C. Teixeira, Carlos F. Beltrán Almeida, Fernando M. Gonçalves, Júlio Gonçalves

J. Electron. Test., 1991

IC Defects-Based Testability Analysis.

José T. de Sousa, Fernando M. Gonçalves, João Paulo Teixeira

Proceedings of the Proceedings IEEE International Test Conference 1991, 1991

1990

A strategy for testability enhancement at layout level.

João Paulo Teixeira, Isabel C. Teixeira, Carlos F. Beltrán Almeida, Fernando M. Gonçalves, Júlio Gonçalves, R. Crespo

Proceedings of the European Design Automation Conference, 1990