Cesar A. Zeferino

According to our database, Cesar A. Zeferino authored at least 42 papers between 2001 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2024

A real-time SVM-based hardware accelerator for hyperspectral images classification in FPGA.

Lucas Amilton Martins, Felipe Viel, Laio Oriel Seman, Eduardo Augusto Bezerra, César Albenes Zeferino

Microprocess. Microsystems, 2024

2023

Hyperspectral Image Classification: An Analysis Employing CNN, LSTM, Transformer, and Attention Mechanism.

Felipe Viel, Renato Cotrim Maciel, Laio Oriel Seman, César Albenes Zeferino, Eduardo Augusto Bezerra, Valderi Reis Quietinho Leithardt

IEEE Access, 2023

Worst-Case Communication Time Analysis for On-Chip Networks With Finite Buffers.

Rubens Vicente De Liz Bomer, César Albenes Zeferino, Laio Oriel Seman, Valderi Reis Quietinho Leithardt

IEEE Access, 2023

2022

A Survey of the RISC-V Architecture Software Support.

Benjamin W. Mezger, Douglas A. dos Santos, Luigi Dilillo, Cesar A. Zeferino, Douglas R. Melo

IEEE Access, 2022

2021

A Hardware Accelerator for Onboard Spatial Resolution Enhancement of Hyperspectral Images.

Felipe Viel, Wemerson Delcio Parreira, Altamiro Amadeu Susin, César Albenes Zeferino

IEEE Geosci. Remote. Sens. Lett., 2021

A Review of Techniques for Implementing Elliptic Curve Point Multiplication on Hardware.

Arielle Verri Lucca, Guilherme A. M. Sborz, Valderi R. Q. Leithardt, Marko Beko, César Albenes Zeferino, Wemerson Delcio Parreira

J. Sens. Actuator Networks, 2021

Characterization of a RISC-V System-on-Chip under Neutron Radiation.

Douglas A. dos Santos, Lucas M. Luza, Maria Kastriotou, Carlo Cazzaniga, Cesar A. Zeferino, Douglas R. Melo, Luigi Dilillo

Proceedings of the 16th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2021

Design and Evaluation of Implementation Impact on a Fault-Tolerant Network-on-Chip Router.

Douglas Rossi Melo, César Albenes Zeferino, Eduardo Augusto Bezerra, Luigi Dilillo

Proceedings of the 16th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2021

2020

An Efficient Interface for the Integration of IoT Devices with Smart Grids.

Felipe Viel, Luis Augusto Silva, Valderi Reis Quietinho Leithardt, Juan Francisco De Paz Santana, Raimundo Celeste Ghizoni Teive, César Albenes Zeferino

Sensors, 2020

Evaluating the CCSDS 123 Compressor Running on RISC-V and ARM Architectures.

Carolina Imianosky, Paulo R. O. Valim, Cesar A. Zeferino, Felipe Viel

Proceedings of the X Brazilian Symposium on Computing Systems Engineering, 2020

A Hardware Accelerator for the Segmentation of Hyperspectral Images.

Arthur Passos, Felipe Viel, Cesar A. Zeferino

Proceedings of the 33rd Symposium on Integrated Circuits and Systems Design, 2020

A Low-Cost Fault-Tolerant RISC-V Processor for Space Systems.

Douglas Almeida dos Santos, Lucas Matana Luza, César Albenes Zeferino, Luigi Dilillo, Douglas Rossi de Melo

Proceedings of the 15th Design & Technology of Integrated Systems in Nanoscale Era, 2020

2019

Maximizing the Inner Resilience of a Network-on-Chip through Router Controllers Design.

Douglas R. Melo, Cesar A. Zeferino, Luigi Dilillo, Eduardo A. Bezerra

Sensors, 2019

<i>RedScarf</i>: an open-source multi-platform simulation environment for performance evaluation of Networks-on-Chip.

Eduardo Alves da Silva, Márcio Eduardo Kreutz, Cesar A. Zeferino

J. Syst. Archit., 2019

A Solution for Controlling and Managing User Profiles based on Data Privacy for IoT Applications.

Valderi R. Q. Leithardt, Douglas A. dos Santos, Luis Augusto Silva, Felipe Viel, Cesar A. Zeferino, Jorge Sá Silva

CoRR, 2019

An Architecture for Delivering Graphical Web Applications in Constrained IoT Devices.

Luiz Fernando Heidrich Duarte, César Albenes Zeferino, Raimundo Celeste Ghizoni Teive

Proceedings of the IX Brazilian Symposium on Computing Systems Engineering, 2019

A custom processor for an FPGA-based platform for automatic license plate recognition.

Guilherme A. M. Sborz, Guilherme A. Pohl, Felipe Viel, Cesar A. Zeferino

Proceedings of the 32nd Symposium on Integrated Circuits and Systems Design, 2019

An SVM-based hardware accelerator for onboard classification of hyperspectral images.

Lucas Amilton Martins, Guilherme A. M. Sborz, Felipe Viel, Cesar A. Zeferino

Proceedings of the 32nd Symposium on Integrated Circuits and Systems Design, 2019

Privacy in the Internet of Things: A Study to Protect User's Data in LPR Systems Using Blockchain.

Iago Sestrem Ochôa, Leonardo Calbusch, Karize Viecelli, Juan F. De Paz, Valderi R. Q. Leithardt, Cesar A. Zeferino

Proceedings of the 17th International Conference on Privacy, Security and Trust, 2019

Analyzing the Error Propagation in a Parameterizable Network-on-Chip Router.

Douglas Rossi de Melo, César Albenes Zeferino, Luigi Dilillo, Eduardo Augusto Bezerra

Proceedings of the IEEE Latin American Test Symposium, 2019

A Low-Cost Hardware Accelerator for CCSDS 123 Predictor in FPGA.

Lucas M. V. Pereira, Douglas A. dos Santos, Cesar A. Zeferino, Douglas R. Melo

Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

2018

Mecanismo de Verificação de Integridade de Software Baseado em BIOS UEFI.

Marciel de Liz Santos, Cesar A. Zeferino, Michelle S. Wangham

Proceedings of the XXXVI Brazilian Symposium on Computer Networks and Distributed Systems, 2018

Analysis of LEON3 systems integration for a Network-on-Chip.

Lucas M. V. Pereira, Douglas R. Melo, Cesar A. Zeferino, Eduardo A. Bezerra

Proceedings of the 19th IEEE Latin-American Test Symposium, 2018

A Hardware Accelerator for Anisotropic Diffusion Filtering in FPGA.

Guilherme F. Weidle, Felipe Viel, Douglas Rossi de Melo, Cesar A. Zeferino

Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

2017

Confidentiality and Authenticity in a Platform Based on Network-on-Chip.

Marcos Roberto Silva, César Albenes Zeferino

Proceedings of the VII Brazilian Symposium on Computing Systems Engineering, 2017

RedScarf: A User-Friendly Multi-Platform Network-on-Chip Simulator.

Eduardo Alves da Silva, Daniel Menegasso, Sergio Vargas, Cesar A. Zeferino

Proceedings of the VII Brazilian Symposium on Computing Systems Engineering, 2017

Deadline, Energy and Buffer-Aware Task Mapping Optimization in NoC-Based SoCs Using Genetic Algorithms.

Jaison Valmor Bruch, Eduardo Alves da Silva, Cesar A. Zeferino, Leandro Soares Indrusiak

Proceedings of the VII Brazilian Symposium on Computing Systems Engineering, 2017

2015

Avaliação Empírica da Proposta Interdisciplinar de Uso dos Processadores BIP.

Paulo Viníccius Vieira, César Albenes Zeferino, André Luís Alice Raabe

Revista Brasileira de Informática na Educ., 2015

2014

Segurança em Redes-em-Chip: Conceitos e Revisão do Estado da Arte.

César Albenes Zeferino, Sidnei Baron, Michelle Silva Wangham

RITA, 2014

XIRU: Interface de Rede Extensível para Integração de Núcleos a uma Rede-em-Chip.

Douglas R. Melo, Michelle S. Wangham, Cesar A. Zeferino

RITA, 2014

Elastic security zones for NoC-based 3D-MPSoCs.

Johanna Sepúlveda, Guy Gogniat, Daniel Florez, Jean-Philippe Diguet, Cesar A. Zeferino, Marius Strum

Proceedings of the 21st IEEE International Conference on Electronics, Circuits and Systems, 2014

2013

Security mechanisms to improve the availability of a Network-on-Chip.

Sidnei Baron, Michelle Silva Wangham, César Albenes Zeferino

Proceedings of the 20th IEEE International Conference on Electronics, 2013

2010

Bipide - Ambiente de Desenvolvimento Integrado para a Arquitetura dos Processadores BIP.

Paulo Viníccius Vieira, André Luís Alice Raabe, César Albenes Zeferino

Revista Brasileira de Informática na Educ., 2010

2009

Adding mechanisms for QoS to a network-on-chip.

Marcelo Daniel Berejuck, César Albenes Zeferino

Proceedings of the 22st Annual Symposium on Integrated Circuits and Systems Design: Chip on the Dunes, 2009

2004

ParIS: a parameterizable interconnect switch for networks-on-chip.

César Albenes Zeferino, Frederico G. M. E. Santo, Altamiro Amadeu Susin

Proceedings of the 17th Annual Symposium on Integrated Circuits and Systems Design, 2004

RASoC: A Router Soft-Core for Networks-on-Chip.

César Albenes Zeferino, Márcio Eduardo Kreutz, Altamiro Amadeu Susin

Proceedings of the 2004 Design, 2004

2003

The Impact of NoC Reuse on the Testing of Core-based Systems.

Érika F. Cota, Márcio Eduardo Kreutz, Cesar A. Zeferino, Luigi Carro, Marcelo Lubaszewski, Altamiro Amadeu Susin

Proceedings of the 21st IEEE VLSI Test Symposium (VTS 2003), 27 April, 2003

SoCIN: A Parametric and Scalable Network-on-Chip.

César Albenes Zeferino, Altamiro Amadeu Susin

Proceedings of the 16th Annual Symposium on Integrated Circuits and Systems Design, 2003

SPIN: A Scalable, Packet Switched, On-Chip Micro-Network.

Adrijean Andriahantenaina, Hervé Charlery, Alain Greiner, Laurent Mortiez, César Albenes Zeferino

Proceedings of the 2003 Design, 2003

2002

A Study on Communication Issues for Systems-on-Chip.

Cesar A. Zeferino, Márcio Eduardo Kreutz, Luigi Carro, Altamiro Amadeu Susin

Proceedings of the 15th Annual Symposium on Integrated Circuits and Systems Design, 2002

2001

Análise e Seleção de Redes de Interconexão para Síntese de Sistemas no Ambiente S3E2S.

Márcio Eduardo Kreutz, César Albenes Zeferino, Luigi Carro, Altamiro Amadeu Susin

RITA, 2001

Communication Architectures for System-on-Chip.

Márcio Eduardo Kreutz, Luigi Carro, Cesar A. Zeferino, Altamiro Amadeu Susin

Proceedings of the 14th Annual Symposium on Integrated Circuits and Systems Design, 2001