Martijn T. Bennebroek

According to our database, Martijn T. Bennebroek authored at least 10 papers between 2003 and 2008.

Collaborative distances:

• Dijkstra number of three.
• Erdős number of four.

2008

Hardwired Networks on Chip in FPGAs to Unify Functional and Con?guration Interconnects.

Kees Goossens, Martijn T. Bennebroek, Jae Young Hur, Muhammad Aqeel Wahlah

Proceedings of the Second International Symposium on Networks-on-Chips, 2008

A Novel Routing Architecture for Field-Programmable Gate-Arrays.

Alexander Danilin, Martijn T. Bennebroek, Sergei Sawitzki

Proceedings of the Architecture of Computing Systems, 2008

2007

Transaction-Based Communication-Centric Debug.

Kees Goossens, Bart Vermeulen, Remco van Steeden, Martijn T. Bennebroek

Proceedings of the First International Symposium on Networks-on-Chips, 2007

Multiplexer-based routing fabric for reconfigurable logic.

Martijn T. Bennebroek, Alexander Danilin

Proceedings of the FPL 2007, 2007

Communication-Centric SoC Debug Using Transactions.

Bart Vermeulen, Kees Goossens, Remco van Steeden, Martijn T. Bennebroek

Proceedings of the 12th European Test Symposium, 2007

2006

Astra: An Advanced Space-Time Reconfigurable Architecture.

Alexander Danilin, Martijn T. Bennebroek, Sergei Sawitzki

Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), 2006

Energy-efficient FPGA interconnect design.

Maurice Meijer, Rohini Krishnan, Martijn T. Bennebroek

Proceedings of the Conference on Design, Automation and Test in Europe: Designers' Forum, 2006

2005

A Novel Toolset for the Development of FPGA-like Reconfigurable Logic.

Alexander Danilin, Martijn T. Bennebroek, Sergei Sawitzki

Proceedings of the 2005 International Conference on Field Programmable Logic and Applications (FPL), 2005

2004

Low energy FPGA interconnect design.

Rohini Krishnan, José Pineda de Gyvez, Martijn T. Bennebroek

Proceedings of the ACM/SIGDA 12th International Symposium on Field Programmable Gate Arrays, 2004

2003

Validation of wire length distribution models on commercial designs.

Martijn T. Bennebroek

Proceedings of the 5th International Workshop on System-Level Interconnect Prediction (SLIP 2003), 2003