Jae Young Hur

Orcid: 0000-0003-4151-908X

According to our database1, Jae Young Hur authored at least 20 papers between 2007 and 2023.

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Bibliography

2023
Page-Size Aware Buddy Allocator With Unaligned Range Supports for TLB Coalescing.
IEEE Access, 2023

2021
Clean-prefetcher: look-ahead prefetching without cache pollution.
IEICE Electron. Express, 2021

2020
Virtual Address Remapping with Configurable Tiles in Image Processing Applications.
IEICE Trans. Inf. Syst., 2020

TLC STT-MRAM aware LLC for multicore processor.
IEICE Electron. Express, 2020

Near-Threshold L1 Data Cache for Yield Management Under Process Variations.
IEEE Access, 2020

Page Table Compaction for TLB Coalescing.
IEEE Access, 2020

2019
Contiguity Representation in Page Table for Memory Management Units.
IEEE Trans. Very Large Scale Integr. Syst., 2019

Block Level TLB Coalescing for Buddy Memory Allocator.
IEICE Trans. Inf. Syst., 2019

Adaptive Linear Address Map for Bank Interleaving in DRAMs.
IEEE Access, 2019

2017
Representing Contiguity in Page Table for Memory Management Units.
Proceedings of the 11th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2017

2012
Customisation of on-chip network interconnects and experiments in field-programmable gate arrays.
IET Comput. Digit. Tech., 2012

Comparative analysis of soft and hard on-chip interconnects for field-programmable gate arrays.
IET Comput. Digit. Tech., 2012

2011
Customizing and hardwiring on-chip interconnects in FPGAs.
PhD thesis, 2011

2010
Design Trade-offs in Customized On-chip Crossbar Schedulers.
J. Signal Process. Syst., 2010

A novel configuration circuit architecture to speedup reconfiguration and relocation for partially reconfigurable devices.
Proceedings of the IEEE 8th Symposium on Application Specific Processors, 2010

2008
Hardwired Networks on Chip in FPGAs to Unify Functional and Con?guration Interconnects.
Proceedings of the Second International Symposium on Networks-on-Chips, 2008

Yeast on a Chip - Single-cell Analyses of MAPK Signaling Pathways in Saccharomyces Cerevisiae using Cell Chips.
Proceedings of the First International Conference on Biomedical Electronics and Devices, 2008

2007
Customizing Reconfigurable On-Chip Crossbar Scheduler.
Proceedings of the IEEE International Conference on Application-Specific Systems, 2007

Partially Reconfigurable Point-to-Point Interconnects in Virtex-II Pro FPGAs.
Proceedings of the Reconfigurable Computing: Architectures, 2007

Systematic Customization of On-Chip Crossbar Interconnects.
Proceedings of the Reconfigurable Computing: Architectures, 2007


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