Bart Vermeulen

According to our database1, Bart Vermeulen authored at least 43 papers between 1999 and 2016.

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Bibliography

2016
Overview of Health Monitoring Techniques for Reliability.
Proceedings of the Workshop on Early Reliability Modeling for Aging and Variability in Silicon Systems, 2016

2014
Transient errors resiliency analysis technique for automotive safety critical applications.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Startup error detection and containment to improve the robustness of hybrid FlexRay networks.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

2012
Architecture and design flow for a debug event distribution interconnect.
Proceedings of the 30th International IEEE Conference on Computer Design, 2012

2011
Interactive Debug of SoCs with Multiple Clocks.
IEEE Design & Test of Computers, 2011

Optimal scheduling of switched FlexRay networks.
Proceedings of the Design, Automation and Test in Europe, 2011

2010
Webcams for Bird Detection and Monitoring: A Demonstration Study.
Sensors, 2010

Obtaining more information from conjoint experiments by best-worst choices.
Computational Statistics & Data Analysis, 2010

INDEXYS, a Logical Step beyond GENESYS.
Proceedings of the Computer Safety, 2010

Obtaining consistent global state dumps to interactively debug systems on chip with multiple clocks.
Proceedings of the IEEE International High Level Design Validation and Test Workshop, 2010

New scan-based test strategy for a dependable many-core processor using a NoC as a Test Access Mechanism.
Proceedings of the 15th European Test Symposium, 2010

A distributed architecture to check global properties for post-silicon debug.
Proceedings of the 15th European Test Symposium, 2010

Switched FlexRay: Increasing the effective bandwidth and safety of FlexRay networks.
Proceedings of 15th IEEE International Conference on Emerging Technologies and Factory Automation, 2010

On-chip Scan-Based Test Strategy for a Dependable Many-Core Processor Using a NoC as a Test Access Mechanism.
Proceedings of the 13th Euromicro Conference on Digital System Design, 2010

2009
A high-level debug environment for communication-centric debug.
Proceedings of the Design, Automation and Test in Europe, 2009

2008
Overview of Debug Standardization Activities.
IEEE Design & Test of Computers, 2008

Functional Debug Techniques for Embedded Systems.
IEEE Design & Test of Computers, 2008

Debugging Distributed-Shared-Memory Communication at Multiple Granularities in Networks on Chip.
Proceedings of the Second International Symposium on Networks-on-Chips, 2008

Integration of Hardware Assertions in Systems-on-Chip.
Proceedings of the 2008 IEEE International Test Conference, 2008

You can catch more bugs with transaction level honey.
Proceedings of the 6th International Conference on Hardware/Software Codesign and System Synthesis, 2008

2007
Debug architecture for the En-II system chip.
IET Computers & Digital Techniques, 2007

Transaction-Based Communication-Centric Debug.
Proceedings of the First International Symposium on Networks-on-Chips, 2007

Communication-Centric SoC Debug Using Transactions.
Proceedings of the 12th European Test Symposium, 2007

A Run-Time Memory Protection Methodology.
Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007

2005
Optimal Interconnect ATPG Under a Ground-Bounce Constraint.
J. Electronic Testing, 2005

Test and debug features of the RTO7 chip.
Proceedings of the Proceedings 2005 IEEE International Test Conference, 2005

2004
Trends in Testing Integrated Circuits.
Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004

Automatic generation of breakpoint hardware for silicon debug.
Proceedings of the 41th Design Automation Conference, 2004

2003
Multi-TAP Controller Architecture for Digital System Chips.
J. Electronic Testing, 2003

Data Invalidation Analysis for Scan-Based Debug on Multiple-Clock System Chips.
J. Electronic Testing, 2003

Minimizing Pattern Count for Interconnect Test under a Ground Bounce Constraint.
IEEE Design & Test of Computers, 2003

Bringing communication networks on a chip: test and verification implications.
IEEE Communications Magazine, 2003

Optimal Interconnect ATPG Under a Ground-Bounce Constraint.
Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003

Creating Value Through Test.
Proceedings of the 2003 Design, 2003

2002
Design for Debug: Catching Design Errors in Digital Chips.
IEEE Design & Test of Computers, 2002

Reducing Time to Volume and Time to Market: Is Silicon Debug and Diagnosis the Answer?
Proceedings of the 20th IEEE VLSI Test Symposium (VTS 2002), Without Testing It's a Gamble, 28 April, 2002

Core-Based Scan Architecture for Silicon Debug.
Proceedings of the Proceedings IEEE International Test Conference 2002, 2002

EEE 1149.1-Compliant Access Architecture for Multiple Core Debug on Digital System Chips.
Proceedings of the Proceedings IEEE International Test Conference 2002, 2002

TAPS All Over My Chips! So Now What Do I Do?
Proceedings of the Proceedings IEEE International Test Conference 2002, 2002

Hierarchical Data Invalidation Analysis for Scan-Based Debug on Multiple-Clock System Chips.
Proceedings of the Proceedings IEEE International Test Conference 2002, 2002

2001
Test and debug strategy of the PNX8525 NexperiaTM digital video platform system chip.
Proceedings of the Proceedings IEEE International Test Conference 2001, Baltimore, MD, USA, 30 October, 2001

2000
Silicon debug of a co-processor array for video applications.
Proceedings of the IEEE International High-Level Design Validation and Test Workshop 2000, 2000

1999
Silicon debug: scan chains alone are not enough.
Proceedings of the Proceedings IEEE International Test Conference 1999, 1999


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