Masato Yoshioka

According to our database, Masato Yoshioka authored at least 9 papers between 2007 and 2014.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2014

A 6-bit, 1-GS/s, 9.9-mW, Interpolated Subranging ADC in 65-nm CMOS.

Takumi Danjo, Masato Yoshioka, Masayuki Isogai, Masanori Hoshino, Sanroku Tsukamoto

IEEE J. Solid State Circuits, 2014

2012

A 6b, 1GS/s, 9.9mW interpolated subranging ADC in 65nm CMOS.

Takumi Danjo, Masato Yoshioka, Masayuki Isogai, Masanori Hoshino, Sanroku Tsukamoto

Proceedings of Technical Program of 2012 VLSI Design, Automation and Test, 2012

2010

A 10-b 50-MS/s 820- μ W SAR ADC With On-Chip Digital Calibration.

Masato Yoshioka, Kiyoshi Ishikawa, Takeshi Takayama, Sanroku Tsukamoto

IEEE Trans. Biomed. Circuits Syst., 2010

A 10b 50MS/s 820µW SAR ADC with on-chip digital calibration.

Masato Yoshioka, Kiyoshi Ishikawa, Takeshi Takayama, Sanroku Tsukamoto

Proceedings of the IEEE International Solid-State Circuits Conference, 2010

Generation of yield-embedded Pareto-front for simultaneous optimization of yield and performances.

Yu Liu, Masato Yoshioka, Katsumi Homma, Toshiyuki Shibuya, Yuzi Kanazawa

Proceedings of the 47th Design Automation Conference, 2010

2009

Find the 'Best' Solution from Multiple Analog Topologies via Pareto-Optimality.

Yu Liu, Masato Yoshioka, Katsumi Homma, Toshiyuki Shibuya

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009

Split capacitor DAC mismatch calibration in successive approximation ADC.

Yanfei Chen, Xiaolei Zhu, Hirotaka Tamura, Masaya Kibune, Yasumoto Tomita, Takayuki Hamada, Masato Yoshioka, Kiyoshi Ishikawa, Takeshi Takayama, Junji Ogawa, Sanroku Tsukamoto, Tadahiro Kuroda

Proceedings of the IEEE Custom Integrated Circuits Conference, 2009

Efficiently finding the 'best' solution with multi-objectives from multiple topologies in topology library of analog circuit.

Yu Liu, Masato Yoshioka, Katsumi Homma, Toshiyuki Shibuya

Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009

2007

A 0.8V 10b 8OMS/s 6.5mW Pipelined ADC with Regulated Overdrive Voltage Biasing.

Masato Yoshioka, Masahiro Kudo, Toshihiko Mori, Sanroku Tsukamoto

Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007