Toshihiko Mori

According to our database, Toshihiko Mori authored at least 27 papers between 1998 and 2022.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2022

Highly power-efficient (2 pJ/bit), 128Gbps 16QAM signal generation of coherent optical DAC transmitter using 28-nm CMOS driver and all-silicon segmented modulator.

Yohei Sobu, Guoxiu Huang, Toshihiko Mori, Yukito Tsunoda, Takuji Yamamoto, Shinsuke Tanaka, Takeshi Hoshida

Proceedings of the Optical Fiber Communications Conference and Exhibition, 2022

2019

Neural-network assistance to calculate precise eigenvalue for fitness evaluation of real product design.

Yukito Tsunoda, Takahiro Notsu, Yasufumi Sakai, Naoki Hamada, Toshihiko Mori, Teruo Ishihara, Atsuki Inoue

Proceedings of the Genetic and Evolutionary Computation Conference Companion, 2019

2018

Error-Free Loopback of a Compact 25 Gb/s × 4 ch WDM Transceiver Assembly Incorporating Silicon (De)Multiplexers with Automated Phase-Error Correction.

Tomoyuki Akiyama, Tsuyoshi Aoki, Takasi Simoyama, Akio Sugama, Shigeaki Sekiguchi, Yohei Sobu, Shinsuke Tanaka, Yu Tanaka, Seok-Hwan Jeong, Motoyuki Nishizawa, Nobuaki Hatori, Akinori Hayakawa, Toshihiko Mori

Proceedings of the Optical Fiber Communications Conference and Exposition, 2018

On-Package High-Density Silicon Photonics Optical Transceiver.

Tsuyoshi Aoki, Shigeaki Sekiguchi, Takasi Simoyama, Shinsuke Tanaka, Motoyuki Nishizawa, Nobuaki Hatori, Yohei Sobu, Akio Sugama, Tomoyuki Akiyama, Akinori Hayakawa, Hidenobu Muranaka, Toshihiko Mori, Y. Chen, Seok-Hwan Jeong, Yu Tanaka, Ken Morito

Proceedings of the European Conference on Optical Communication, 2018

2017

Low crosstalk simultaneous 12 ch × 25 Gb/s operation of high-density silicon photonics multichannel receiver.

Tsuyoshi Aoki, Tomoyuki Akiyama, Akio Sugama, Akinori Hayakawa, Hidenobu Muranaka, Takasi Simoyama, Shinsuke Tanaka, Motoyuki Nishizawa, Nobuaki Hatori, Yohei Sobu, Yanfei Chen, Toshihiko Mori, Shigeaki Sekiguchi, Seok-Hwan Jeong, Yu Tanaka, Ken Morito

Proceedings of the Optical Fiber Communications Conference and Exhibition, 2017

Ultra-Low-Power (1.59 mW/Gbps), 56-Gbps PAM4 Operation of Si Photonic Transmitter Integrating Segmented PIN Mach-Zehnder Modulator and 28-nm CMOS Driver.

Shinsuke Tanaka, Takasi Simoyama, Tsuyoshi Aoki, Toshihiko Mori, Shigeaki Sekiguchi, Seok-Hwan Jeong, Tatsuya Usuki, Yu Tanaka, Ken Morito

Proceedings of the European Conference on Optical Communication, 2017

Low Crosstalk Simultaneous 16-channel × 25 Gb/s Operation of High Density Silicon Photonics Optical Transceiver.

Tsuyoshi Aoki, Shigeaki Sekiguchi, Takasi Simoyama, Shinsuke Tanaka, Motoyuki Nishizawa, Nobuaki Hatori, Yohei Sobu, Akio Sugama, Tomoyuki Akiyama, Akinori Hayakawa, Hidenobu Muranaka, Toshihiko Mori, Yanfei Chen, Seok-Hwan Jeong, Yu Tanaka, Ken Morito

Proceedings of the European Conference on Optical Communication, 2017

2016

A 28.3 Gb/s 7.3 pJ/bit 35 dB backplane transceiver with eye sampling phase adaptation in 28 nm CMOS.

Hiroki Miyaoka, Futoshi Terasawa, Masahiro Kudo, Hideki Kano, Atsushi Matsuda, Noriaki Shirai, Shigeaki Kawai, Takayuki Shibasaki, Takumi Danjo, Yuuki Ogata, Yasufumi Sakai, Hisakatsu Yamaguchi, Toshihiko Mori, Yoichi Koyanagi, Hirotaka Tamura, Yutaka Ide, Kazuhiro Terashima, Hirohito Higashi, Tomokazu Higuchi, Naoaki Naka

Proceedings of the 2016 IEEE Symposium on VLSI Circuits, 2016

24 to 34-Gb/s ×4 multi-rate VCSEL-based optical transceiver with referenceless CDR.

Yukito Tsunoda, Takayuki Shibasaki, Hideki Oku, Jun Matsui, Takashi Shiraishi, Satoshi Ide, Toshihiko Mori, Yoichi Koyanagi, Hirotaka Tamura

Proceedings of the Optical Fiber Communications Conference and Exhibition, 2016

3.5 A 56Gb/s NRZ-electrical 247mW/lane serial-link transceiver in 28nm CMOS.

Takayuki Shibasaki, Takumi Danjo, Yuuki Ogata, Yasufumi Sakai, Hiroki Miyaoka, Futoshi Terasawa, Masahiro Kudo, Hideki Kano, Atsushi Matsuda, Shigeaki Kawai, Tomoyuki Arai, Hirohito Higashi, Naoaki Naka, Hisakatsu Yamaguchi, Toshihiko Mori, Yoichi Koyanagi, Hirotaka Tamura

Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

2015

25.78-Gb/s VCSEL-based optical transceiver with retimer-embedded driver and receiver ICs.

Yukito Tsunoda, Takayuki Shibasaki, Hideki Oku, Satoshi Ide, Toshihiko Mori, Yoichi Koyanagi, Kazuhiro Tanaka, Tomohiro Ishihara, Hirotaka Tamura

Proceedings of the Optical Fiber Communications Conference and Exhibition, 2015

A 25 Gbps silicon photonic transmitter and receiver with a bridge structure for CPU interconnects.

Akinori Hayakawa, Masaya Kibune, Asako Toda, Shinsuke Tanaka, Takasi Simoyama, Yanfei Chen, Tomoyuki Akiyama, Shigekazu Okumura, Takeshi Baba, Tomoyuki Akahoshi, Seiji Ueno, Kazunori Maruyama, Masahiko Imai, Jian Hong Jiang, Pradip Thachile, Tamer Riad, Shigeaki Sekiguchi, Suguru Akiyama, Yu Tanaka, Ken Morito, Daisuke Mizutani, Toshihiko Mori, Takuji Yamamoto, Hiroji Ebe

Proceedings of the Optical Fiber Communications Conference and Exhibition, 2015

22.8 A 24-to-35Gb/s x4 VCSEL driver IC with multi-rate referenceless CDR in 0.13um SiGe BiCMOS.

Yukito Tsunoda, Takayuki Shibasaki, Satoshi Ide, Toshihiko Mori, Yoichi Koyanagi, Kazuhiro Tanaka, Tomohiro Ishihara, Hirotaka Tamura

Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

22.7 4×25.78Gb/s retimer ICs for optical links in 0.13μm SiGe BiCMOS.

Takayuki Shibasaki, Yukito Tsunoda, Hideki Oku, Satoshi Ide, Toshihiko Mori, Yoichi Koyanagi, Kazuhiro Tanaka, Tomohiro Ishihara, Hirotaka Tamura

Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

22.2 A 25Gb/s hybrid integrated silicon photonic transceiver in 28nm CMOS and SOI.

Yanfei Chen, Masaya Kibune, Asako Toda, Akinori Hayakawa, Tomoyuki Akiyama, Shigeaki Sekiguchi, Hiroji Ebe, Nobuhiro Imaizumi, Tomoyuki Akahoshi, Suguru Akiyama, Shinsuke Tanaka, Takasi Simoyama, Ken Morito, Takuji Yamamoto, Toshihiko Mori, Yoichi Koyanagi, Hirotaka Tamura

Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

2014

A 1.95 GHz Fully Integrated Envelope Elimination and Restoration CMOS Power Amplifier Using Timing Alignment Technique for WCDMA and LTE.

Kazuaki Oishi, Eiji Yoshida, Yasufumi Sakai, Hideki Takauchi, Yoichi Kawano, Noriaki Shirai, Hideki Kano, Masahiro Kudo, Tomotoshi Murakami, Tetsuro Tamura, Shigeaki Kawai, Kazuo Suto, Hiroshi Yamazaki, Toshihiko Mori

IEEE J. Solid State Circuits, 2014

A 56-Gb/s receiver front-end with a CTLE and 1-tap DFE in 20-nm CMOS.

Takayuki Shibasaki, Win Chaivipas, Yanfei Chen, Yoshiyasu Doi, Takayuki Hamada, Hideki Takauchi, Toshihiko Mori, Yoichi Koyanagi, Hirotaka Tamura

Proceedings of the Symposium on VLSI Circuits, 2014

3.2 A 1.95GHz fully integrated envelope elimination and restoration CMOS power amplifier with envelope/phase generator and timing aligner for WCDMA and LTE.

Kazuaki Oishi, Eiji Yoshida, Yasufumi Sakai, Hideki Takauchi, Yoichi Kawano, Noriaki Shirai, Hideki Kano, Masahiro Kudo, Tomotoshi Murakami, Tetsuro Tamura, Seitaro Kawai, Shinji Yamaura, Kazuo Suto, Hiroshi Yamazaki, Toshihiko Mori

Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

2012

A fully integrated triple-band CMOS power amplifier for WCDMA mobile handsets.

Kouichi Kanda, Yoichi Kawano, Takao Sasaki, Noriaki Shirai, Tetsuro Tamura, Shigeaki Kawai, Masahiro Kudo, Tomotoshi Murakami, Hiroyuki Nakamoto, Nobumasa Hasegawa, Hideki Kano, Nobuhiro Shimazui, Akiko Mineyama, Kazuaki Oishi, Masashi Shima, Naoyoshi Tamura, Toshihide Suzuki, Toshihiko Mori, Kimitoshi Niratsuka, Shinji Yamaura

Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

A real-time temperature-compensated CMOS RF on-chip power detector with high linearity for wireless applications.

Hiroyuki Nakamoto, Masahiro Kudo, Kimitoshi Niratsuka, Toshihiko Mori, Shinji Yamaura

Proceedings of the 38th European Solid-State Circuit conference, 2012

2010

SAR ADC Algorithm with Redundancy and Digital Error Correction.

Tomohiko Ogawa, Haruo Kobayashi, Yosuke Takahashi, Nobukazu Takai, Masao Hotta, Hao San, Tatsuji Matsuura, Akira Abe, Katsuyoshi Yagi, Toshihiko Mori

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2010

Non-binary SAR ADC with digital error correction for low power applications.

Tomohiko Ogawa, Tatsuji Matsuura, Haruo Kobayashi, Nobukazu Takai, Masao Hotta, Hao San, Akira Abe, Katsuyoshi Yagi, Toshihiko Mori

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2010

2007

A 0.8V 10b 8OMS/s 6.5mW Pipelined ADC with Regulated Overdrive Voltage Biasing.

Masato Yoshioka, Masahiro Kudo, Toshihiko Mori, Sanroku Tsukamoto

Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

2003

A CMOS multichannel 10-Gb/s transceiver.

Hideki Takauchi, Hirotaka Tamura, Satoshi Matsubara, Masaya Kibune, Yoshiyasu Doi, Takaya Chiba, Hideaki Anbutsu, Hisakatsu Yamaguchi, Toshihiko Mori, Motomu Takatsu, Kohtaroh Gotoh, Toshiaki Sakai, Takeshi Yamamura

IEEE J. Solid State Circuits, 2003

1999

Customization Rule Generation for Electronic Sales Promotion System in Wholesale Industry.

Masaki Yumoto, Kyungsuk Oh, Norihisa Komoda, Toshihiko Mori

Proceedings of the First International Workshop on Advance Issues of E-Commerce and Web-Based Information Systems, 1999

1998

Low-power SRAM design using half-swing pulse-mode techniques.

Kenneth W. Mai, Toshihiko Mori, Bharadwaj S. Amrutur, Ron Ho, Bennett Wilburn, Mark A. Horowitz, Isao Fukushi, Tetsuo Izawa, Shin Mitara

IEEE J. Solid State Circuits, 1998

A charge-transfer amplifier and an encoded-bus architecture for low-power SRAM's.

Shoichiro Kawashima, Toshihiko Mori, Ryuhei Sasagawa, Makoto Hamaminato, Shigetoshi Wakayama, Kazuo Sukegawa, Isao Fukushi

IEEE J. Solid State Circuits, 1998