Toshiyuki Shibuya

According to our database1, Toshiyuki Shibuya authored at least 18 papers between 1990 and 2019.

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Bibliography

2019
Foreword.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2019

Conference Reports: Recap of the 24th Asia and South Pacific Design Automation Conference.
IEEE Des. Test, 2019

2013
A 32Gb/s wireline receiver with a low-frequency equalizer, CTLE and 2-tap DFE in 28nm CMOS.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

2011
A New Strategy for Simultaneous Escape Based on Boundary Routing.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011

A 4-channel 10.3Gb/s transceiver with adaptive phase equalizer for 4-to-41dB loss PCB channel.
Proceedings of the IEEE International Solid-State Circuits Conference, 2011

2010
"Condition-based" dummy fill insertion method based on ECP and CMP predictive models.
Proceedings of the 11th International Symposium on Quality of Electronic Design (ISQED 2010), 2010

B-escape: a simultaneous escape routing algorithm based on boundary routing.
Proceedings of the 2010 International Symposium on Physical Design, 2010

Generation of yield-embedded Pareto-front for simultaneous optimization of yield and performances.
Proceedings of the 47th Design Automation Conference, 2010

2009
Efficient Power Network Analysis Considering Multidomain Clock Gating.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009

Find the 'Best' Solution from Multiple Analog Topologies via Pareto-Optimality.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009

Efficiently finding the 'best' solution with multi-objectives from multiple topologies in topology library of analog circuit.
Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009

2008
Finding the Worst Voltage Violation in Multi-Domain Clock Gated Power Network.
Proceedings of the Design, Automation and Test in Europe, 2008

Non-Gaussian Statistical Timing models of die-to-die and within-die parameter variations for full chip analysis.
Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008

2007
Fast power network analysis with multiple clock domains.
Proceedings of the 25th International Conference on Computer Design, 2007

2005
Panel I: who is responsible for the design for manufacturability issues in the era of nano-technologies?
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

2003
PDL: A New Physical Synthesis Methodology.
Proceedings of the 4th International Symposium on Quality of Electronic Design (ISQED 2003), 2003

1997
Large scale circuit partitioning with loose/stable net removal and signal flow based clustering.
Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, 1997

1990
Touch and Cross Router.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 1990


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