Takayuki Hamada

According to our database1, Takayuki Hamada authored at least 7 papers between 2002 and 2017.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2017
Inferring win-lose product network from user behavior.
Proceedings of the International Conference on Web Intelligence, 2017

2014
A 56-Gb/s receiver front-end with a CTLE and 1-tap DFE in 20-nm CMOS.
Proceedings of the Symposium on VLSI Circuits, 2014

2010
A 3 Watt 39.8-44.6 Gb/s Dual-Mode SFI5.2 SerDes Chip Set in 65 nm CMOS.
IEEE J. Solid State Circuits, 2010

A Dynamic Offset Control Technique for Comparator Design in Scaled CMOS Technology.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2010

Split Capacitor DAC Mismatch Calibration in Successive Approximation ADC.
IEICE Trans. Electron., 2010

A 5Gb/s transceiver with an ADC-based feedforward CDR and CMA adaptive equalizer in 65nm CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010

2002
Using Symbolic Model Checking to Detect Service Interactions in Telecommunication Services.
Proceedings of the Information Networking, 2002


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