Masaya Hamada

According to our database, Masaya Hamada authored at least 2 papers between 2024 and 2026.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2026

A 3-nm FinFET 563-kbit 35.5-Mbit/mm² Dual-Rail SRAM With 3.89-pJ/Access High Energy Efficient and 27.5-μW/Mbit One-Cycle Latency Low-Leakage Mode.

Yumito Aoyagi, Koji Nii, Makoto Yabuuchi, Tomotaka Tanaka, Kazuto Mizutani, Masaya Hamada, Yuichiro Ishii, Yen Chi Chou, Jun Cheng Liu, Chien-Yu Huang, Kang-Hui Peng, Yu-Hao Hsu, Isabel Wang, Hong-Chen Cheng, Hung-Jen Liao, Tsung-Yung Jonathan Chang

IEEE J. Solid State Circuits, April, 2026

2024

A 3nm Fin-FET 19.87-Mbit/mm² 2RW Pseudo Dual-Port 6T SRAM with High-R Wire Tracking and Sequential Access Aware Dynamic Power Reduction.

Tomotaka Tanaka, Yuichiro Ishii, Makoto Yabuuchi, Yumito Aoyagi, Masaya Hamada, Kazuto Mizutani, Koji Nii, Hidehiro Fujiwara, Isabel Wang, Hong-Chen Cheng, Hung-Jen Liao, Tsung-Yung Jonathan Chang

Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024