Hung-Jen Liao
According to our database1,
Hung-Jen Liao
authored at least 27 papers
between 2000 and 2021.
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Bibliography
2021
A 7-nm Compute-in-Memory SRAM Macro Supporting Multi-Bit Input, Weight and Output and Achieving 351 TOPS/W and 372.4 GOPS.
IEEE J. Solid State Circuits, 2021
A 5-nm 135-Mb SRAM in EUV and High-Mobility Channel FinFET Technology With Metal Coupling and Charge-Sharing Write-Assist Circuitry Schemes for High-Density and Low-V<sub>MIN</sub> Applications.
IEEE J. Solid State Circuits, 2021
2020
15.1 A 5nm 135Mb SRAM in EUV and High-Mobility-Channel FinFET Technology with Metal Coupling and Charge-Sharing Write-Assist Circuitry Schemes for High-Density and Low-VMIN Applications.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020
15.3 A 351TOPS/W and 372.4GOPS Compute-in-Memory SRAM Macro in 7nm FinFET CMOS for Machine-Learning Applications.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020
2019
A 290-mV, 7-nm Ultra-Low-Voltage One-Port SRAM Compiler Design Using a 12T Write Contention and Read Upset Free Bit-Cell.
IEEE J. Solid State Circuits, 2019
A 7nm 2.1GHz Dual-Port SRAM with WL-RC Optimization and Dummy-Read-Recovery Circuitry to Mitigate Read- Disturb-Write Issue.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019
2018
A 290MV Ultra-Low Voltage One-Port SRAM Compiler Design Using a 12T Write Contention and Read Upset Free Bit-Cell in 7NM FinFET Technology.
Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018
2017
12.3 A low-power and high-performance 10nm SRAM architecture for mobile applications.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017
12.1 A 7nm 256Mb SRAM in high-k metal-gate FinFET technology with write-assist circuitry for low-VMIN applications.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017
2016
Wirel. Commun. Mob. Comput., 2016
A 16nm dual-port SRAM with partial suppressed word-line, dummy read recovery and negative bit-line circuitries for low VMIN applications.
Proceedings of the 2016 IEEE Symposium on VLSI Circuits, 2016
A 64-Kb 0.37V 28nm 10T-SRAM with mixed-Vth read-port and boosted WL scheme for IoT applications.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2016
2015
A 16 nm 128 Mb SRAM in High-κ Metal-Gate FinFET Technology With Write-Assist Circuitry for Low-VMIN Applications.
IEEE J. Solid State Circuits, 2015
17.2 A 64kb 16nm asynchronous disturb current free 2-port SRAM with PMOS pass-gates for FinFET technologies.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015
2014
Proceedings of the 2014 International Test Conference, 2014
13.5 A 16nm 128Mb SRAM in high-κ metal-gate FinFET technology with write-assist circuitry for low-VMIN applications.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014
A configurable 2-in-1 SRAM compiler with constant-negative-level write driver for low Vmin in 16nm Fin-FET CMOS.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2014
2013
An Offset-Tolerant Fast-Random-Read Current-Sampling-Based Sense Amplifier for Small-Cell-Current Nonvolatile Memory.
IEEE J. Solid State Circuits, 2013
A 20nm 112Mb SRAM in High-к metal-gate with assist circuitry for low-leakage and low-VMIN applications.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013
2012
Compact Measurement Schemes for Bit-Line Swing, Sense Amplifier Offset Voltage, and Word-Line Pulse Width to Characterize Sensing Tolerance Margin in a 40 nm Fully Functional Embedded SRAM.
IEEE J. Solid State Circuits, 2012
2011
A Large Sigma V <sub>TH</sub> /VDD Tolerant Zigzag 8T SRAM With Area-Efficient Decoupled Differential Sensing and Fast Write-Back Scheme.
IEEE J. Solid State Circuits, 2011
An offset-tolerant current-sampling-based sense amplifier for Sub-100nA-cell-current nonvolatile memory.
Proceedings of the IEEE International Solid-State Circuits Conference, 2011
2010
A Differential Data-Aware Power-Supplied (D <sup>2</sup> AP) 8T SRAM Cell With Expanded Write/Read Stabilities for Lower VDDmin Applications.
IEEE J. Solid State Circuits, 2010
2009
A 0.6 V Dual-Rail Compiler SRAM Design on 45 nm CMOS Technology With Adaptive SRAM Power for Lower VDD_min VLSIs.
IEEE J. Solid State Circuits, 2009
2007
Proceedings of the 2007 IEEE International SOC Conference, 2007
2000
Proceedings of the 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, 2000